Semiconductor device for electrostatic discharge protection
View Patent ↗The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater. The high resistance of the natively doped region can achieve the trigger voltage with a smaller ESD current leaking through, which decreases the size of the ESD protection device and increases its performance and sensitivity. Thus, the invention provides for more robust and cost effective ESD protection devices.
1. A semiconductor electrostatic discharge (ESD) protection device comprising:
a substrate having an upper portion and a lower portion;
a first well and a second well formed in the upper portion of the substrate;
a natively doped region in the upper portion of the substrate, between the first well and the second well, having substantially the same doping as the lower portion of the substrate;
a discharge circuit formed in the first well to create a discharge path for the electrostatic current generated during an ESD event; and
an ESD voltage trigger consisting of the natively doped region provided between the first well and the second well, the natively doped region having a resistance at least about 10 times higher than the resistance of the first and second wells such that when current passes through during the ESD event, a voltage across the ESD voltage trigger triggers the discharge circuit, the voltage being proportional to a width of the natively doped region;
the substrate, the natively doped region and the first and second wells being of a first connectivity type, and the substrate and the natively doped region having substantially the same doping.
2. The device of claim 1 , wherein the second well includes a diffusion of the same connectivity type.
3. The device of claim 2 , wherein the second well further comprises a third well of the first connectivity type separating the diffusion of the second well and the natively doped region.
4. The device of claim 1 , wherein the natively doped region is an epitaxial layer.
5. The device of claim 1 , wherein the discharge circuit comprises two implanted regions of a second connectivity type opposite the first connectivity type.
6. The device of claim 5 , wherein the first connectivity type is P type and the second connectivity type is N type.
7. The device of claim 5 , wherein the first connectivity type is N type and the second connectivity type is P type.
8. The device of claim 1 , further comprising a plurality of discharge circuits formed in the first well.
9. The device of claim 1 , wherein the natively doped region is provided in the form of a ring around the first well, and wherein the wells are ring shaped.
10. The device of claim 1 , wherein the natively doped region is provided in the form of one or more strips, and wherein the first and second wells are electrically connected to each other to form one well.
11. The device of claim 1 , wherein the resistance of the natively doped region is in the range of 10 to 100 times higher than the resistance of the first and second wells.
12. The device of claim 1 , wherein the resistance of the natively doped region is more than 100 times higher than the resistance of the first and second wells.
13. The device of claim 5 , wherein the two implanted regions are diffusions, and the discharge circuit is a parasitic bipolar device dominantly of the second connectivity type, thus forming a snap-back device.
14. The device of claim 13 , wherein the parasitic bipolar device is formed under a MOS structure.
15. The device of claim 13 , further comprising a fixed potential drop element placed in series with the discharge circuit for increasing either or both of the holding and trigger voltages to an operable value.
16. The device of claim 15 , wherein the fixed potential drop element is a diode.
17. The device of claim 5 , wherein one of the implanted regions is a diffusion and the other implanted region is a discharge circuit well of the second connectivity type;
the diffusion of the discharge circuit defining a first bipolar transistor with the first well and the discharge circuit well, the first bipolar transistor being dominantly of the second connectivity type;
the discharge circuit well comprising one diffusion of the first connectivity type and another diffusion of the second connectivity type; and
the diffusion of the discharge circuit well that is of the first connectivity type defining a second bipolar transistor dominantly of the first connectivity type with the first well and the discharge circuit well, the collector of the second bipolar transistor being connected to the base of the first bipolar transistor and vice versa, thus forming a silicon controlled rectifier.
18. A semiconductor electrostatic discharge (ESD) protection device comprising:
a substrate having an upper portion and a lower portion;
a first well formed in the upper portion of the substrate including a first diffusion;
a second well formed in the upper portion of the substrate including a second diffusion;
a natively doped region in the upper portion of the substrate, between the first well and the second well, having substantially the same doping as the lower portion of the substrate;
an ESD voltage trigger consisting of the natively doped region separating the first and the second wells, the natively doped region having a resistance at least about 10 times higher than the resistance of the first and the second wells; and
a third well formed in the second well including third and fourth diffusions;
the substrate, the first and second wells, the natively doped region, the first and the third diffusions being of a first connectivity type, and the third well, the second and the fourth diffusions being of a second connectivity type;
the second diffusion forming a first bipolar transistor dominantly of the second connectivity type with the second well and the third well, the third diffusion forming a second bipolar transistor dominantly of the first connectivity type with the third well and the second well; the collector of the second bipolar transistor being connected to the base of the first bipolar transistor and vice versa, thus forming a silicon controlled rectifier that activates by a current leaking from the first well across the ESD voltage trigger in an ESD event.
19. A semiconductor electrostatic discharge (ESD) protection device comprising:
a substrate having an upper portion and a lower portion;
a first well formed in the upper portion of the substrate including a first diffusion;
a second well formed in the upper portion of the substrate including second and third diffusions;
a natively doped region in the upper portion of the substrate, between the first well and the second well, having substantially the same doping as the lower portion of the substrate; and
an ESD voltage trigger consisting of the natively doped region separating the first and the second wells, the natively doped region having a resistance at least about 10 times higher than the resistance of the first and the second wells;
the substrate, the first and second wells, the natively doped region, and the first diffusion being of a first connectivity type, and the second and third diffusions being of a second connectivity type; the second and the third diffusions forming a bipolar transistor dominantly of the second connectivity type, thus forming a snapback device that activates by a current leaking from the first well across the ESD voltage trigger in an ESD event.