System and method for multiengine operation with super descriptor in SAS/SATA controller wherein portion of super-descriptor is executed without intervention of initiator
View Patent ↗A method of chaining a plurality of engines for a system on chip (SOC) controller device and a SOC controller device are disclosed herein. The method comprises: generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller; passing the super-descriptor from the initiator to a first engine of the plurality of engines; and executing a portion of the super-descriptor at each of the plurality of engines in series without the intervention of the initiator.
1. A method of chaining a plurality of engines for a system on chip (SOC) controller device, the method comprising:
generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller;
passing the super-descriptor from the initiator to a first engine of the plurality of engines; and
executing a portion of the super-descriptor at each of the plurality of engines in series without the intervention of the initiator.
2. The method of claim 1 , wherein the initiator comprises a hardware block.
3. The SOC controller device of claim 1 , wherein the initiator comprises a processor.
4. The SOC controller device of claim 3 , wherein the processor includes firmware.
5. The method of claim 1 , further comprising passing the super-descriptor between each engine of the plurality of engines in series.
6. The method of claim 1 , wherein the first engine passes the super-descriptor to a second engine by writing a pointer to a queue in a global shared memory, the queue corresponding the second engine, the pointer pointing to the super-descriptor.
7. The method of claim 1 , wherein the super-descriptor comprises a plurality of descriptors, each descriptor comprising instructions for at least one of the engines of the plurality of engines.
8. The method of claim 1 , wherein the super-descriptor specifies a loop in which the super-descriptor is passed to at least one of the engines of the plurality of engines at least twice.
9. The method of claim 1 , wherein the SOC controller device comprises a RAID controller.
10. The method of claim 1 , wherein the SOC controller device comprises a host bus adapter.
11. A system on chip (SOC) controller device, comprising:
a plurality of engines, for carrying out the operations specified by a super descriptor; and
an initiator configured to:
generate a super-descriptor for providing instructions to the plurality of engines, the super descriptor specifying a series of operations to be carried out by the plurality of engines without the intervention of the initiator; and
pass the super-descriptor to a first engine of the plurality of engines.
12. The SOC controller device of claim 11 , wherein the initiator comprises a hardware block.
13. The SOC controller device of claim 11 , wherein the initiator comprises a processor.
14. The SOC controller device of claim 13 , wherein the processor includes firmware.
15. The SOC controller device of claim 11 , wherein the plurality of engines are configured to pass the super-descriptor between each other in series.
16. The SOC controller device of claim 11 , further comprising a global shared memory; wherein the first engine passes the super-descriptor to a second engine by writing a pointer to a queue in the global shared memory, the queue corresponding the second engine, the pointer pointing to the super-descriptor.
17. The SOC controller device of claim 11 , wherein the super-descriptor comprises a plurality of descriptors, each descriptor comprising instructions for at least one of the engines of the plurality of engines.
18. The SOC controller device of claim 11 , wherein the super-descriptor specifies a loop in which the super-descriptor is passed to at least one of the engines of the plurality of engines at least twice.
19. The SOC controller device of claim 11 , wherein the SOC controller device comprises a RAID controller.
20. The SOC controller device of claim 11 , wherein the SOC controller device comprises a host bus adapter.