Analog finite impulse response adaptation method and apparatus
A SerDes receiver comprising: an input for receiving a signal, the signal having a baud rate; an Analog Finite Impulse Response equalizer (AFIR) for equalizing the received signal, the AFIR comprising: a pre-cursor tap having a pre-cursor coefficient; a cursor tap having a cursor coefficient, the cursor coefficient being constrained to a non-negative value; and a post-cursor tap having a post-cursor coefficient; an adaptation block coupled to the AFIR, the adaptation block configured to adjust the pre-cursor coefficient and the post-cursor coefficient based on the received signal, the adaptation block further being configured to constrain the values of the pre-cursor and post-cursor coefficients to be non-positive.
1. A SerDes receiver comprising:
an input for receiving a signal, the signal having a baud rate;
an Analog Finite Impulse Response equalizer (AFIR) for equalizing the received signal, the AFIR comprising:
a pre-cursor tap having a pre-cursor coefficient;
a cursor tap having a cursor coefficient, the cursor coefficient being constrained to a non-negative value; and
a post-cursor tap having a post-cursor coefficient;
an equalizer adaptation block coupled to the AFIR, the equalizer adaptation block configured to adjust the pre-cursor coefficient and the post-cursor coefficient based on the received signal, the adaptation block further being configured to constrain the values of the pre-cursor and post-cursor coefficients to be non-positive;
wherein the sum of the pre-cursor, cursor, and post-cursor coefficients is constrained to be greater than K, wherein K is greater than 0.
2. The SerDes receiver of claim 1 , further comprising a variable gain amplifier (VGA) for amplifying the received signal.
3. The SerDes receiver of claim 2 , wherein the cursor coefficient is set to a fixed value.
4. The SerDes receiver of claim 3 , wherein the fixed value is 1.
5. The SerDes receiver of claim 2 , wherein an input the VGA is coupled to an output of the AFIR for amplifying the received signal after equalization.
6. The SerDes receiver of claim 2 , wherein an output of the VGA is coupled to an input of the AFIR for amplifying the received signal prior to equalization.
7. The SerDes receiver of claim 1 , wherein K is selected based on a maximum peaking gain of the AFIR, according to the relationship:
=
2
C
10
(
MaxPeakingGain
dB
/
20
)
+
1
,
wherein C is a cursor coefficient value.
8. The SerDes receiver of claim 4 , wherein K is selected based on a maximum peaking gain of the AFIR, according to the relationship:
K
=
2
10
(
MaxPeakingGain
dB
/
20
)
+
1
.
9. The SerDes receiver of claim 1 , further comprising a digitizing block for digitizing the equalized signal.
10. The SerDes receiver of claim 9 , wherein the digitizing block comprises an analog to digital converter.
11. The SerDes receiver of claim 9 , wherein the digitizing block comprises a slicer.