Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation
View Patent ↗A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.
1. A method of assembling a codeword in a forward error correction system having K information bits in a total of N bits, the method comprising:
obtaining K/2 home column information bits from a home column of an information bit array;
obtaining K/2 away column information bits from a selected number of away columns of the information bit array, the selected number of away columns consisting of information bit array columns other than the home column;
combining the K/2 home column information bits with the K/2 away column information bits to assemble K information bits;
calculating N−K redundant parity bits associated with the assembled K information bits according to an error control code; and
appending the N−K redundant parity bits to the assembled K information bits to assemble the codeword valid under the error control code.
2. The method of claim 1 , further comprising prepending padding bits to the assembled K information bits.
3. The method of claim 1 , wherein the K/2 home column information bits and the K/2 away column information bits are combined in an alternating manner to assemble the K information bits.
4. The method of claim 1 wherein obtaining the K/2 away column information bits comprises following a diagonal progression through the selected number of away columns that skips the home column.
5. The method of claim 1 wherein obtaining the K/2 away column information bits comprises following a diagonal progression through the selected number of away columns that skips the home column and one or more columns adjacent to the home column.
6. The method of claim 1 wherein obtaining the K/2 away column information bits begins at a first away column adjacent the home column.
7. The method of claim 1 wherein combining the K/2 home column information bits and the K/2 away column information bits comprises interleaving the K/2 home column information bits and the K/2 away column information bits to assemble the K information bits.
8. The method of claim 1 wherein the error control code is a BCH (Bose, Chaudhuri, and Hocquenghem) code.
9. An encoder comprising:
an information bit array assembly module for assembling information bits into an information bit array; and
a codeword assembly module for assembling a codeword in a forward error correction system having K information bits in a total on N bits by:
obtaining K/2 home column information bits form a home column of the information bit array;
obtaining K/2 away column information bits from a selected number of away columns of the information bit array, the away columns consisting of information bit array columns other than the home column; and,
combining the K/2 home column information bits with the K/2 away column information bits to assemble K information bits;
calculating N−K redundant parity bits associated with the assembled K information bits according to an error control code; and
appending the N−K redundant parity bits to the assembled K information bits to assemble the codeword valid under the error control code.
10. The encoder of claim 9 , wherein the codeword assembly module prepends padding bits to the assembled K information bits.
11. The encoder of claim 9 , wherein the Error Control Code is a BCH (Bose, Chaudhuri, and Hocquenghem) code.
12. The encoder of claim 9 , wherein the K/2 home column information bits and the K/2 away column information bits are combined in an alternating manner to assemble the K information bits.
13. The encoder of claim 9 , wherein the codeword assembly module comprises a plurality of programmable shift registers to store the information bits during assembly of the codeword.
14. The encoder of claim 13 , wherein the plurality of programmable shift registers interleave the K/2 home column information bits and the K/2 away column information bits to assemble the K information bits.
15. The encoder of claim 9 , further comprising:
a codeword array assembly module for assembling a plurality of codewords associated with the information bits into an information codeword array.
16. The encoder of claim 15 , further comprising:
a parity bit array assembly module for assembling the N−K redundant parity bits into a parity bit array; and
a parity codeword array assembly module for assembling a plurality of parity codewords associated with the information bits into a parity codeword array.
17. The encoder of claim 16 , further comprising:
a parity on parity array assembly module for assembling parity on parity bits into a parity on parity bit array, the parity on parity bits being associated with the N−K redundant parity bits.
18. The encoder of claim 17 , further comprising:
a framing module for combing the information codeword array, the parity codeword array, and the parity on parity array into an encoded message block.