Circuit and method for real-time monitoring of process, temperature, and voltage variations
The present disclosure provides a monitoring system for monitoring the operation of an integrated circuit, the monitoring system comprising: a reference circuit comprising a reference signal delay path and an output for outputting a reference signal; a monitoring circuit, the monitoring circuit comprising: a programmable delay line for providing a controllably selectable delay path; and an output for outputting a delayed signal; a comparison circuit, for comparing the reference signal to the delayed signal and determining whether the error has occurred based on the comparison.
1. A monitoring system for monitoring the operation of an integrated circuit, the monitoring system comprising:
a reference circuit comprising a first register and a first inverter coupled in a first feedback loop to provide a reference signal delay path having a first setup margin, and an output for outputting a reference signal;
a monitoring circuit, the monitoring circuit comprising:
a second register;
a second inverter;
a programmable delay line;
wherein the second register, the programmable delay line, and the second inverter are coupled in a feedback loop to provide a controllably selectable delay path having a controllably selectable second setup margin; and
an output for outputting a delayed signal; and
a comparison circuit, for comparing the output reference signal to the output delayed signal and determining whether a time setup error has occurred based on the comparison.
2. The monitoring system of claim 1 , wherein the programmable delay line comprises a plurality of buffers and multiplexers coupled to each other such that a number of buffers in the delay line is controllably selectable.
3. The monitoring system of claim 1 , further comprising an auto calibrator circuit coupled to the programmable delay line for calibrating the programmable delay line.
4. The monitoring system of claim 3 , wherein the monitoring system is configured to:
set a delay length of the programmable delay line;
compare the delay signal to the reference signal;
if a value of the delay signal does not match a value of the reference signal, then:
incrementally increase the delay length; and
for each value of the delay length, compare the delay signal to the reference signal;
record the delay length when either value of the delay signal does not match a value of the reference signal or a maximum value of the delay length is reached.
5. The monitoring system of claim 3 , wherein the monitoring system is configured to:
set a delay length of the delay line;
compare the delay signal to the reference signal;
if a value of the delay signal does not match a value of the reference signal, then:
incrementally decrease the delay length; and
for each value of the delay length, compare the delay signal to the reference signal;
record the delay length when either value of the delay signal does not match a value of the reference signal or a minimum value of the delay length is reached.
6. A method of monitoring the operation of an integrated circuit, the method comprising:
providing a reference circuit on the integrated circuit, the reference circuit comprising a first register and a first inverter coupled in a first feedback loop to provide a reference signal delay path having a first setup margin, and an output for outputting a reference signal;
providing a monitoring circuit on the integrated circuit, the monitoring circuit comprising:
a second register;
a second inverter;
a programmable delay line;
wherein the second register, the programmable delay line, and the second inverter are coupled in a feedback loop to provide a controllably selectable delay path having a controllably selectable second setup margin; and
an output for outputting a delayed signal;
setting a delay length of the programmable delay line;
providing power to the integrated circuit; and
comparing the output reference signal and the output delay signal to determine whether a time setup error has occurred.
7. The method of claim 6 , wherein providing power to the integrated circuit comprises powering up a power gated region of the integrated circuit.
8. The method of claim 6 , further comprising determining that an error has occurred if a value of the delay signal does not match a value of the reference signal.
9. The method of claim 8 , further comprising:
if an error has not occurred, incrementally adjusting the delay length of the programmable delay line; and
periodically comparing the reference signal and delay signal.
10. The method of claim 9 , further comprising:
if an error has occurred, estimating a voltage drop experienced by a power gated region based on the delay length of the programmable delay line.
11. The method of claim 9 , wherein the initial value of the delay line length is a maximum delay line length of the programmable delay line and the delay length is incrementally reduced.
12. The method of claim 9 , wherein the initial value of the delay line length is a minimum delay line length of the programmable delay line and the delay length is incrementally increased.