System and method for boost floor mitigation

1. An Error Correction Code (ECC) decoder including at least one processor, the at least one processor comprising:

a detection element for detecting a floor error condition;

a check node circuit element;

a delay element coupled in a feedback loop with the check node element;

a first gain element coupled to an output of the check node element, the gain element being enabled when the detection element has detected a floor error condition;

a feedback clearing element coupled to the delay element, the feedback clearing element configured to clear the delay element when a floor error condition has been detected; and

a Log Likelihood Ratio (LLR) scaling device to scale down a current LLR state in a FEC block.

2. The decoder of claim 1 , wherein the first gain element is enabled only for low rank columns of an H matrix, a low rank column being a column having a weight of 2 or less.

3. The decoder of claim 1 , wherein the processor comprises a layered processor.

4. The decoder of claim 1 , wherein the ECC code is a Low Density Parity Check (LPDC) code.

5. The decoder of claim 3 , further comprising:

a memory element for storing a full FEC block to be processed;

a plurality of shift processors for performing a circulant shift operation specified by an H matrix;

wherein the layered processor comprises a plurality of layered processors, each layered processor further comprising:

a port for receiving a value from a column in the H matrix;

a subtractor coupled to the port, the subtractor configured to remove previous extrinsic information for a layer from a value received from the H matrix, an output of the subtractor being coupled to an input of the check node circuit element;

an adder for combining the check node input and an output of the check node;

wherein the delay element stores the check node output for use in a subsequent iteration.

6. The decoder of claim 5 , wherein the first gain element is coupled between the output of the check node element and an input of the adder; and wherein an input of the delay element is coupled to an output of the first gain element.

7. The decoder of claim 5 , wherein the first gain element is coupled between the output of the check node element and an input of the adder; and wherein an input of the delay element is coupled to the output of the check node element.

8. The decoder of claim 7 , further comprising a second gain element between an output of the delay element and an input of the subtractor.

9. The decoder of claim 8 , wherein the first gain element is enabled only for low rank columns of the H matrix, a low rank column being a column having a weight of 2 or less.

10. The decoder of claim 1 , wherein the detection element is configured to:

count a number of failing check nodes;

when the number of failing check nodes falls below a first threshold, count a number of consecutive layers the failing checknodes are below the first threshold; and

determine that a floor error condition has occurred when the number of counted consecutive layers is above a second threshold.

11. The decoder of claim 10 , wherein the decoder is configured to downscale Log Likelihood Ratio (LLR) values stored in a main memory of the decoder when a floor error condition has occurred.

12. A method for boost floor mitigation during a decoding operation performed by a decoder, the method comprising:

monitoring for a floor error condition while performing the decoding operation;

if a floor error condition has been detected, then:

clearing a feedback delay memory in the decoder;

downscaling Log Likelihood Ratio (LLR) values stored in a main memory of the decoder;

applying a gain in low-rank columns; and

continuing to perform the decoding operation.

13. The method of claim 12 , wherein the decoding operation is an Error Correction Code (ECC) decoding operation.

14. The method of claim 13 , wherein the ECC code comprises a Low Density Parity Check (LPDC) code.

15. The method of claim 12 , wherein monitoring for a floor error condition comprises:

counting a number of failing check nodes;

when the number of failing check nodes falls below a first threshold, counting a number of consecutive layers the failing checknodes are below the first threshold; and

determining that a floor error condition has occurred when the number of counted consecutive layers is above a second threshold.