Self-synchronous scrambler/descrambler and method for operating same

1. A self-synchronous scrambler/descrambler, comprising

an M-bit Scrambler State memory for retaining M previously scrambled/descrambled bits;

a SOP/EOP Zero Inserter for receiving a bus word of a frame, and for replacing all bytes of the bus word which are excluded from scrambling/descrambling with a value of zero;

a Mid-Packet Word Logic, in communication with the SOP/EOP Inserter and the M-bit Scrambler State memory, for receiving bits from the SOP/EOP Zero Inserter, and scrambling/descrambling the received bits using the previously scrambled/descrambled bits from the M-bit Scrambler State memory; and

a Barrel Shifter, in communication with the Mid-Packet Word Logic and the M-bit Scrambler State memory, for rotating the M-bit Scrambler State memory backwards an amount equal to (N×8) modulo M bits, where N is the number of bytes of the bus word which were replaced with the value of zero by the SOP/EOP Zero Inserter.

2. The self-synchronous scrambler of claim 1 , wherein the bus word is a SOP Word.

3. The self-synchronous scrambler of claim 2 , wherein the bytes of the bus word excluded from scrambling/descrambling are the Core Header bytes.

4. The self-synchronous scrambler of claim 1 , wherein the bus word is an EOP Word.

5. The self-synchronous scrambler of claim 1 , wherein the bytes of the bus word excluded from scrambling/descrambling are a remainder of bytes of the bus word after a last byte of a payload frame check sequence, and the Core Header bytes of a next frame.

6. A method for scrambling/descrambling bits, comprising

receiving a bus word of a frame in a SOP/EOP Zero Inserter;

replacing, with the SOP/EOP Zero Inserter, bytes of the bus word which are excluded from scrambling/descrambling with a value of zero;

scrambling/descrambling bits of the bus word with a Mid-Packet Word Logic by exclusive-ORing with previously scrambled/descrambled bits from an M-Bit Scrambler State memory;

retaining the scrambled/descrambled bits of the bus word in the M-Bit Scrambler State memory; and

rotating the scrambled/descrambled bits of the bus word backwards an amount equal to (N×8) modulo M bits, where N is the number of bytes of the bus word which were replaced with the value of zero.

7. The method of claim 6 , wherein the bus word is a SOP Word.

8. The method claim 7 , wherein the bytes of the bus word excluded from scrambling/descrambling are a remainder of bytes in the bus word after the last bytes of a payload frame check sequence.

9. The method of claim 7 , wherein the bytes of the bus word excluded from scrambling/descrambling are a remainder of bytes of the bus word after the last bytes of a payload frame check sequence, and the Core Header bytes of a next frame.

10. The method of claim 6 , wherein the bus word is an EOP Word.

11. The method of claim 10 , wherein the bytes of the bus word excluded from scrambling/descrambling are a remainder of bytes in the bus word after a last byte of a payload frame check sequence.

12. The method of claim 10 , wherein the bytes of the bus word excluded from scrambling/descrambling are the Core Header bytes.