Transmit virtual concatenation processor
View Patent ↗A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192 and STS-768. The processor supports virtual concatenation with arbitrary channel mapping at both STS-1 and STS-3c granularities. The processor also supports contiguous concatenation with STS-12c, STS-24c, STS-48c, STS-192c, etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS-3c-Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation. The processor terminates the H 1 , H 2 and H 3 bytes in the line overhead of a SONET/SDH frame and inserts the multi-frame indicator and sequence number in the H 4 byte of the path overhead.
1. A system for multiplexing input data from a plurality of channels onto a selected one of a plurality of SONET/SDH frames having different sizes, comprising:
a calendar configured to selectively multiplex the input data received from the plurality of channels;
a processor configured to receive the multiplexed input data and re-arrange the multiplexed input data onto the selected SONET/SDH frame using virtual concatenation or contiguous concatenation or a combination of both; and
a terminator configured to terminate overhead bytes within the selected SONET/SDH frame, wherein the processor further comprises:
an input RAM configured to receive and output the multiplexed input data;
a crossbar configured to receive and re-arrange the multiplexed input data outputted from the input RAM;
an output RAM configured to receive the re-arranged multiplexed data from the crossbar; and
a copy machine configured to control and coordinate operation of the input RAM, the crossbar and the output RAM, wherein the copy machine is further configured to control and coordinate the operation of the input RAM, the crossbar and the output RAM in accordance with a schedule; wherein the overhead bytes include sequence numbers; and wherein the calendar, the schedule and the sequence numbers are each double buffered and switched in a predetermined sequence so as to allow hitless re-provisioning.
2. The system according to claim 1 wherein the copy machine is paused when the overhead bytes are inserted into the selected SONET/SDH frame.
3. The system according to claim 1 wherein the input RAM comprises a plurality of memory banks.
4. The system according to claim 1 wherein the input RAM is triple buffered thereby allowing the system to support a fixed latency from data request to data available.
5. The system according to claim 4 wherein the fixed latency is up to N cycles for STS-N traffic.
6. The system according to claim 1 wherein the processor is further configured to handle arbitrary virtual concatenation with STS-1 or STS-3 granularity.
7. The system according to claim 1 wherein the processor is further configured to handle contiguous concatenation with STS-Nc capacity, where N is a multiple of 3.
8. The system according to claim 1 wherein the processor is further configured to handle non-standard virtual concatenation and one or more proprietary concatenation formats.
9. The system according to claim 1 wherein the processor is configured to handle mixed concatenation of one or more contiguous concatenation traffic and virtual concatenation traffic with STS-3c granularity.
10. The system according to claim 1 wherein the system is implemented in a programmable logic device.
11. The system according to claim 1 wherein the processor is further configured to receive and process the overhead bytes; and the system further comprising:
a shifter configured to redistribute the overhead bytes and the input data received from the plurality of channels before the overhead bytes and the input data are selectively directed by the calendar to the processor.
12. The system according to claim 11 wherein the processor is configured to handle one or more mixed concatenation including STS-1-Xv.
13. The system according to claim 1 wherein the overhead bytes terminated by the terminator include H 1 , H 2 and H 3 bytes in line overhead and H 4 byte in path overhead.
14. The system according to claim 13 wherein a multi-frame indicator and a sequence number are inserted into the H 4 byte in the path overhead.
15. The system according to claim 1 wherein the different sizes of the plurality of SONET/SDH frames include STS-12, STS-48, STS-192 and STS-768.