IP Library Granted Patent US 8,990,661
Granted Patent B1
US 8,990,661 · App. 13/785,848 · Granted Mar 24, 2015

Layer specific attenuation factor LDPC decoder

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Quick Facts
Patent No.
US 8,990,661
App. No.
13/785,848
Granted
Mar 24, 2015
Kind
B1
Abstract

A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing the normalized layered min-sum algorithm wherein the attenuation factor of the min-sum algorithm is determined by the coefficients of the attenuation factor matrix.

Claims (34)

1. An LDPC decoder for decoding low-density parity check (LDPC) encoded data, the LDPC encoded data comprising a plurality of log-likelihood ratios (LLRs), each of the plurality of LLRs representing one of a plurality of bits of an LDPC codeword encoded using a parity check matrix having a plurality of layers, the decoder comprising:

an attenuation factor matrix comprising a plurality of coefficients, each of the plurality of coefficients identifying a layer specific attenuation factor for each layer of the plurality of layers of the parity check matrix;

a check node processor coupled to the attenuation factor matrix, the check node processor having circuitry for performing check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing a layered min-sum algorithm having at least one layer specific attenuation factor associated with at least one layer of the parity check matrix;

a variable node processor coupled to the check node processor, the variable node processor having circuitry for performing variable node processing for each layer of the parity check matrix; and

a codeword estimate check processor coupled to the variable node processor, the codeword estimate check processor having circuitry for performing a check of the estimate of the LDPC encoded codeword to determine if the codeword estimate is a codeword.

2. The LDPC decoder of claim 1 , wherein the plurality of coefficients are stored in a lookup table.

3. The LDPC decoder of claim 2 , wherein the decoding may be performed over multiple iterations and wherein the layer specific attenuation factor matrix includes coefficients for a first iteration and a second iteration, at least some of the coefficients for the first iteration different from the coefficients for the second iteration.

4. A method for decoding low-density parity check (LDPC) encoded data, the method comprising:

receiving a plurality of log-likelihood ratios (LLRs) at a decoder, each of the plurality of LLRs representing one of a plurality of bits of an LDPC codeword encoded using a parity check matrix having a plurality of layers;

decoding the LLRs utilizing an attenuation factor matrix and a normalized layered min-sum decoding process to provide an estimate of the LDPC encoded codeword, the attenuation factor matrix including coefficients identifying attenuation factors for two or more of the layers of the parity check matrix.

5. The method of claim 4 , wherein the attenuation factor matrix includes a coefficient for each of the layers of the parity check matrix.

6. The method of claim 4 , wherein the layers of the parity check matrix include a first layer and a second layer, the coefficient for the first layer different from the coefficient for the second layer.

7. The method of claim 6 , wherein the decoding may be performed over multiple iterations and wherein the attenuation factor matrix includes coefficients for a first iteration and a second iteration, at least some of the coefficients for the first iteration different from the coefficients for the second iteration.

8. The method of claim 6 wherein the attenuation factor matrix includes coefficients for each iteration of the decoding process.

9. The method of claim 6 wherein the attenuation factor matrix includes a coefficient for each layer of the parity check matrix and each iteration of the decoding process.

10. The method of claim 4 , wherein decoding the LLRs further comprises:

performing check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing a normalized layered min-sum algorithm having at least one layer specific attenuation factor associated with at least one layer of the parity check matrix;

performing variable node processing for each layer of the parity check matrix; and

performing a check of the estimate of the LDPC encoded codeword to determine if the codeword estimate is a codeword.

11. The method of claim 10 , further comprising, after performing a check of the estimate of the LDPC encoded codeword to determine if the codeword estimate is a codeword:

if the codeword estimate is a codeword, outputting the codeword estimate from the decoder; and

if the codeword estimate is not a codeword, initiating another iteration of the decoding process beginning with performing check node processing.

12. The method of claim 11 , where each layer is identified as one or more circulant rows in the parity check matrix associated with the LDPC encoded codeword.

13. An LDPC decoder for decoding low-density parity check (LDPC) encoded data, the LDPC encoded data comprising a plurality of log-likelihood ratios (LLRs), each of the plurality of LLRs representing one of a plurality of bits of an LDPC codeword encoded using a parity check matrix having a plurality of layers, the decoder comprising circuitry for decoding the LLRs utilizing an attenuation factor matrix and a normalized layered min-sum decoding process to provide an estimate of the LDPC encoded codeword, the attenuation factor matrix including coefficients identifying attenuation factors for two or more of the layers of the parity check matrix.

14. The LDPC decoder of claim 13 , wherein the attenuation factor matrix includes a coefficient for each of the layers of the parity check matrix.

15. The LDPC decoder of claim 13 , wherein the layers of the parity check matrix include a first layer and a second layer, the coefficient for the first layer different from the coefficient for the second layer.

16. The LDPC decoder of claim 15 , wherein the decoding may be performed over multiple iterations and wherein the attenuation factor matrix includes coefficients for a first iteration and a second iteration, at least some of the coefficients for the first iteration different from the coefficients for the second iteration.

17. The LDPC decoder of claim 15 wherein the attenuation factor matrix includes coefficients for each iteration of the decoding process.

18. The LDPC decoder of claim 15 wherein the attenuation factor matrix includes a coefficient for each layer of the parity check matrix and each iteration of the decoding process.

19. The LDPC decoder of claim 13 , wherein the circuitry for decoding the LLRs further comprises:

a check node processor having circuitry for performing check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing a normalized layered min-sum algorithm having at least one layer specific attenuation factor associated with at least one layer of the parity check matrix;

a variable node processor coupled to the check node processor, the variable node processor having circuitry for performing variable node processing for each layer of the parity check matrix; and

a codeword estimate check processor coupled to the variable node processor, the codeword estimate check processor having circuitry for performing a check of the estimate of the LDPC encoded codeword to determine if the codeword estimate is a codeword.

20. The LDPC decoder of claim 19 , wherein the decoder further comprises circuitry for outputting the codeword estimate from the decoder if the codeword estimate is a codeword and for initiating another iteration of the decoding process beginning with performing check node processing if the codeword estimate is not a codeword.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
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From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (US), INC.
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CHANGE OF NAME Recorded Mar 1, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
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PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: PMC-SIERRA US, INC.
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From: MARELLI, ALESSIA; MICHELONI, RINO; NORRIE, CHRISTOPHER I. W.; ONUFRYK, PETER Z.
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