IP Library Assignment 038102/0874
Patent Assignment
Reel/Frame 038102/0874

Corrective Assignment to Correct the Assignee Name and Address Previously Recorded at Reel: 037961 Frame: 0519. Assignor(S) Hereby Confirms the Change of Name.

Recorded: 2016-03-15 Pages: 10
Assignor
PMC-SIERRA US, INC.
Executed: 2016-01-15
Assignee
MICROSEMI STORAGE SOLUTIONS (US), INC.
ONE ENTERPRISE, ALISO VIEJO, CALIFORNIA, 92656
Covered Properties (50)
Method of Tracking Arrival Order of Packets into Plural Queues
Patent: 9,467,307 →
Application: 12/200,062 →
Publication: US 2010/0054268
Nonvolatile Memory Controller with Two-Stage Error Correction Technique for Enhanced Reliability
Patent: 8,707,122 →
Application: 13/023,336 →
Nonvolatile Memory Controller with Host Controller Interface for Retrieving and Dispatching Nonvolatile Memory Commands in a Distributed Manner
Patent: 8,588,228 →
Application: 13/052,008 →
Interrupt Technique for a Nonvolatile Memory Controller
Patent: 8,554,968 →
Application: 13/052,388 →
System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique
Patent: 8,601,346 →
Application: 13/052,835 →
System and Method for Routing a Data Message Through a Message Network
Patent: 8,656,071 →
Application: 13/107,265 →
Apparatus and Method to Adjust Power and Performance of Integrated Circuits
Patent: 9,824,773 →
Application: 13/159,330 →
Data Regeneration Apparatus and Method for Pci Express
Patent: 8,599,913 →
Application: 13/195,685 →
Error Correction Code Technique for Improving Read Stress Endurance
Patent: 8,694,855 →
Application: 13/287,443 →
Shuffler Error Correction Code System and Method
Patent: 8,694,849 →
Application: 13/330,573 →
Nonvolatile Memory Controller with Concatenated Error Correction Codes
Patent: 8,656,257 →
Application: 13/434,770 →
Nonvolatile Memory Controller with Error Detection for Concatenated Error Correction Codes
Patent: 8,621,318 →
Application: 13/435,572 →
Method and Apparatus for an Aggregated Non-Transparent Requester Id Translation for a Pcie Switch
Patent: 8,917,734 →
Application: 13/681,257 →
Flexible Routing Engine for a Pci Express Switch and Method of Use
Patent: 9,025,495 →
Application: 13/743,225 →
Method and Apparatus for Translated Routing in an Interconnect Switch
Patent: 8,995,302 →
Application: 13/743,281 →
Method and Apparatus for Mapped I/O Routing in an Interconnect Switch
Patent: 9,146,890 →
Application: 13/750,991 →
Apparatus and Method for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System Using Strong Log-Likelihood (Llr) Values
Patent: 9,128,858 →
Application: 13/752,757 →
Apparatus and Method Based on Ldpc Codes for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System
Patent: 9,092,353 →
Application: 13/752,885 →
Layer Specific Attenuation Factor Ldpc Decoder
Patent: 8,990,661 →
Application: 13/785,848 →
System and Method for Lifetime Specific Ldpc Decoding
Patent: 9,397,701 →
Application: 13/792,831 →
System and Method for Adaptive Check Node Approximation in Ldpc Decoding
Patent: 8,935,598 →
Application: 13/797,444 →
System and Method for Reduced Memory Storage in Ldpc Decoding
Patent: 8,984,365 →
Application: 13/860,300 →
System and Method for Avoiding Error Mechanisms in Layered Iterative Decoding
Patent: 8,984,376 →
Application: 13/860,411 →
System and Method with Reference Voltage Partitioning for Low Density Parity Check Decoding
Patent: 9,235,467 →
Application: 14/165,135 →
Publication: US 2014/0281823
System and Method for Random Noise Generation
Patent: 9,235,488 →
Application: 14/168,222 →
Publication: US 2014/0281762
System and Method for Higher Quality Log Likelihood Ratios in Ldpc Decoding
Patent: 9,590,656 →
Application: 14/210,067 →
Publication: US 2014/0281800
System and Method for Accumulating Soft Information in Ldpc Decoding
Patent: 9,454,414 →
Application: 14/210,971 →
Publication: US 2014/0281828
System and Method for Memory Block Pool Wear Leveling
Patent: 9,417,804 →
Application: 14/325,212 →
Publication: US 2016/0004458
Nonvolatile Memory System That Uses Programming Time to Reduce Bit Errors
Patent: 9,305,661 →
Application: 14/475,757 →
Publication: US 2016/0064096
High Quality Log Likelihood Ratios Determined Using Two-Index Look-Up Table
Patent: 9,450,610 →
Application: 14/557,214 →
Parallel Replica Cdr to Correct Offset and Gain in a Baud Rate Sampling Phase Detector
Patent: 9,344,272 →
Application: 14/605,884 →
Layer Specific Attenuation Factor Ldpc Decoder
Application: 14/628,212 →
Apparatus and Method for Minimizing Exclusive-or (Xor) Computation Time
Patent: 9,477,562 →
Application: 14/694,986 →
Nonvolatile Memory System with Retention Monitor
Application: 14/715,403 →
Layer Specific Ldpc Decoder
Patent: 9,813,080 →
Application: 14/747,042 →
Memory Controller and Integrated Circuit Device for Correcting Errors in Data Read from Memory Cells
Patent: 9,448,881 →
Application: 14/747,952 →
Nonvolatile Memory System with Read Circuit for Performing Reads Using Threshold Voltage Shift Read Instruction
Patent: 9,799,405 →
Application: 14/812,891 →
Nonvolatile Memory System with Program Step Manager and Method for Program Step Management
Patent: 9,899,092 →
Application: 15/042,125 →
Publication: US 2017/0213597
High Performance Bch Error Correction Circuits
Application: 61/374,216 →
Non Volatile Memory Host Controller Interface Device
Application: 61/374,242 →
Error Correction Control Architecture for Reliable SSD
Application: 61/585,627 →
System and Method for Avoiding Error Mechanisms in Layered Iterative Decoding
Application: 61/781,873 →
System and Method for Ldpc Decoding Having Reduced Memory Storage Requirements
Application: 61/782,263 →
Additive-White-Gaussian_Noise Generation on an FPGA or ASIC
Application: 61/792,124 →
Optimal Threshold Placement for LDPC
Application: 61/792,591 →
System and Method for Higher Quality Log Likelihood Ratios in Ldpc Decoding
Application: 61/793,198 →
System and Method for Accumulating Soft Information in Ldpc Decoding
Application: 61/794,750 →
Nonvolatile Memory System with Erase Suspend Circuit and Method for Erase Suspend Management
Application: 62/266,261 →
Nonvolatile Memory with Shared Algorithm Mode
Application: 62/274,715 →
Nonvolatile Memory System with Program Step Manager and Method for Program Step Management
Application: 62/287,570 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 18, 2011
From: ONUFRYK, PETER Z.; PATEL, JAYESH; JASER, IHAB; SESHAN, GANESH T.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 025984/0478 →
Assignment of Assignor's Interest Mar 21, 2011
From: ONUFRYK, PETER Z; LEVIT, INNA
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 025992/0514 →
Assignment of Assignor's Interest Mar 21, 2011
From: ONUFRYK, PETER Z; PATEL, JAYESH; JASER, IHAB
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 025988/0934 →
Assignment of Assignor's Interest Nov 19, 2012
From: BROWN, DAVID ALAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029324/0252 →
Assignment of Assignor's Interest Jan 16, 2013
From: BROWN, DAVID ALAN; ONUFRYK, PETER Z.; TALLEDO, CESAR
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029644/0486 →
Assignment of Assignor's Interest Jan 16, 2013
From: BROWN, DAVID ALAN; ONUFRYK, PETER Z.; TALLEDO, CESAR
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029644/0255 →
Assignment of Assignor's Interest Jan 25, 2013
From: BROWN, DAVID ALAN; ONUFRYK, PETER Z.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029699/0371 →
Assignment of Assignor's Interest Jan 29, 2013
From: MARELLI, ALESSIA; MICHELONI, RINO; NORRIE, CHRISTOPHER I. W.; JASER, IHAB
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029714/0155 →
Assignment of Assignor's Interest Jan 29, 2013
From: MARELLI, ALESSIA; MICHELONI, RINO; NORRIE, CHRISTOPHER I. W.; ONUFRYK, PETER Z.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029713/0328 →
Assignment of Assignor's Interest Jul 19, 2013
From: PMC-SIERRA US, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 030832/0604 →
Corrective Assignment to Correct the Conveying and Receiving Parties Previously Recorded on Reel 030832 Frame 0604. Assignor(S) Hereby Confirms the Conveying Party Data: Integrated Device Technology, Inc. Teceiving: Pmc-Sierra Us, Inc. Jul 23, 2013
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: PMC-SIERRA US, INC.
Reel/Frame 030919/0040 →
Security Interest in Patents Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
Assignment of Assignor's Interest Jan 27, 2014
From: MARELLI, ALESSIA; ONUFRYK, PETER Z.; MICHELONI, RINO
To: PMC-SIERRA US, INC.
Reel/Frame 032126/0916 →
Release of Security Interest Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
Patent Security Agreement Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
Change of Name Mar 1, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 037961/0519 →
Change of Name Jul 15, 2016
From: PMC-SIERRA INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 039173/0560 →
Assignment of Assignor's Interest Aug 7, 2017
From: MICROSEMI SOLUTIONS (U.S.), INC.
To: IP GEM GROUP, LLC
Reel/Frame 043212/0001 →
Change of Name Aug 7, 2017
From: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
To: MICROSEMI SOLUTIONS (U.S.), INC.
Reel/Frame 043458/0351 →
Release of Security Interest May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
Security Interest Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
Security Interest Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
Security Interest Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
Release of Security Interest May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
Reel/Frame 053466/0011 →
Security Interest Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →