Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values
View Patent ↗Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.
1. An integrated circuit device for correcting errors in data read from memory cells, comprising:
an encoder, the encoder is configured from a single parity check matrix; the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero; and
a decoder, the decoder is configured from the single parity check matrix; the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value, wherein a code-rate that the encoder and decoder uses is changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.
2. The integrated circuit device of claim 1 , further comprising:
a data management module, the data management module is connected with the decoder and the encoder, the data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing the code-rate.
3. The integrated circuit device of claim 1 , further comprising:
a communication link, the communication link connects the encoder and the decoder, wherein information on a number of errors occurring during decode cause a code-rate adjustment.
4. The integrated circuit device of claim 1 , wherein the strong LLR value for the bits set in the decoder is selected from the group consisting of a value that is strongly resistant to change, a value that is fixed during the decoding, and a guard value.
5. The integrated circuit device of claim 2 , wherein the number of bits set to zero in the encoder is selected from the group consisting of a fraction of a processing engine width and a multiple of a processing engine width.
6. The integrated circuit device of claim 2 , wherein the number of bits set to a strong LLR value in the decoder is selected from the group consisting of a fraction of a processing engine width and a multiple of a processing engine width.
7. The integrated circuit device of claim 2 , wherein a code used to develop the single parity check matrix is selected from the group consisting of a user specified error correcting code, a Reed-Solomon code, a Bose-Chaudhuri-Hochquenghem (BCH) code, a quasi-cyclic low density parity check code (QC-LDPC), an irregular repeat-accumulate (IRA) code, a code from projective geometry, and a user defined quasi-cyclic code.
8. The integrated circuit device of claim 1 , wherein a memory cell is selected from the group consisting of NAND, NOR, user defined.
9. The integrated circuit device of claim 8 , wherein the memory cell is selected from the group consisting of a single-level cell, a triple-level cell, and a multi-level cell.
10. The integrated circuit device of claim 2 , wherein the code-rate is changed when a number of bits corrected by the decoder crosses a threshold and the threshold is less than the correctable raw bit error rate limit.
11. The integrated circuit device of claim 10 , wherein the threshold prevents a potential decoding failure by maintaining the number of bits corrected by the decoder at a level below the correctable raw bit error rate limit.
12. The integrated circuit device of claim 2 , further comprising;
a RAID architecture, the RAID architecture is used to recover data if the data fails to decode successfully.
13. A method for correcting errors in data read from memory cells, comprising:
making a virtual adjustment to an encoder, wherein the encoder is configured from a single low density parity check (LDPC) matrix, the making sets a number of bits in the encoder to zero; and
encoding data while using the number of bits set to zero to virtually reduce a dimension of the encoder, wherein a code-rate is established; and
decoding the encoded data at a decoder configured from the single parity check matrix, wherein a code-rate that the encoder and decoder uses is changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to a strong log-likelihood ratio (LLR) value.
14. The method of claim 13 , further comprising:
receiving a command to change the code-rate from a first code-rate to a second code-rate, wherein data is encoded at the second code-rate in response to the receiving.
15. The method of claim 14 , wherein the command to change the code-rate is based on information that occurred during a previous decode operation performed by a decoder.
16. The method of claim 15 , wherein information further comprises:
a number of bits corrected during the previous decode operation.
17. The method of claim 13 , wherein the code-rate is changed when a number of bits corrected by a decoder crosses a threshold and the threshold is less than a correctable raw bit error rate limit of the code-rate.
18. The method of claim 17 , wherein the threshold prevents a potential decoding failure by maintaining the number of bits corrected by the decoder at a level below the correctable raw bit error rate limit.
19. The method of claim 13 , further comprising;
using a RAID function to recover data following a decode failure.
20. A method for correcting errors in data read from memory cells, comprising:
making a virtual adjustment to a decoder, the decoder is configured from a single parity check matrix, wherein the making assigns a strong log-likelihood ratio (LLR) value to a number of bits in the decoder; and
decoding data while using the strong LLR value for the number of bits, wherein the strong LLR value changes a code-rate used during the decoding by virtually adjusting a column dimension of the single parity check matrix.
21. The method of claim 20 , further comprising:
sending a command to change a code-rate used to encode data from a first code-rate to a second code-rate, wherein data is encoded at the second code-rate in response to the sending.
22. The method of claim 21 , wherein the command to change code-rate is based on information that occurred during the decoding.
23. The method of claim 22 , wherein information further comprises:
a number of bits corrected during the decoding.
24. The method of claim 20 , wherein the strong LLR value is selected from the group consisting of a value that is strongly resistant to change, a value that is fixed during the decoding, and a guard value.
25. The integrated circuit device of claim 1 , wherein a code used to develop the single parity check matrix is a low density parity check (LDPC) code.
26. The method of claim 13 , wherein the code used to develop the LDPC matrix is a quasi-cyclic LDPC code.
27. The method of claim 20 , wherein a code used to develop the single parity check matrix is a low density parity check code (LDPC).