Patent Assignment
Reel/Frame 030832/0604
Assignment of Assignor's Interest
Recorded: 2013-07-19
Pages: 15
Assignor
PMC-SIERRA US, INC.
Executed: 2013-07-12
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
6042 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Properties
(75)
Apparatus and Method for Determining Byte Gain and Loss Adjustments in a Sonet/Sdh Network Element
Method and System for Error Correction Over Serial Link
Patent:
6,748,567 →
Application:
09/846,875 →
Network Switch Port with Weighted Random Early Discard
Network Switch Port Traffic Manager Having Configurable Packet and Cell Servicing
Fair Weighted Queuing Bandwidth Allocation System for Network Switch Port
Back Pressure Control System for Network Switch Port
Multiservice Switching System with Distributed Switch Fabric
Patent:
7,079,485 →
Application:
09/847,711 →
Method and Apparatus for Scheduling Static and Dynamic Traffic Through a Switch Fabric
Apparatus and Method for Reordering Sequence Indicated Information Units into Proper Sequence
Traffic Manager for Network Switch Port
Buffer Manager for Network Switch Port
Multicast Cell Buffer for Network Switch
Programmably Sliceable Switch-Fabric Unit and Methods of Use
Patent:
7,263,097 →
Application:
09/997,478 →
Variably Delayable Transmission of Packets Between Independently Clocked Source, Intermediate, and Destination Circuits While Maintaining Orderly and Timely Processing in One or Both of the Intermediate and Destination Circuits
Patent:
7,181,485 →
Application:
09/997,507 →
Method and System for Error Correction Over Serial Link
Expansion of Cross-Domain Addressing for Pci-Express Packets Passing Through Non-Transparent Bridge
Automated Device Testing Using Intertwined Stimulus-Generation and Response Validation Specifications for Managing Dut's That Generate Out-of-Order Responses
Device and Method for Address Matching with Post Matching Limit Check and Nullification
Patent:
7,779,197 →
Application:
11/382,475 →
Binary Base Address Sorting Method and Device with Shift Vector
Patent:
7,647,438 →
Application:
11/382,480 →
Packets Transfer Device Having Data Absorbing Buffers with Elastic Buffer Capacities
Binary Base Address Search Device and Method
Patent:
7,454,554 →
Application:
11/395,715 →
Method and Device for Base Address Sorting and Entry into Base Address Registers
Patent:
7,694,025 →
Application:
11/395,918 →
Device for Concurrent Limit Validity Check
Patent:
7,634,586 →
Application:
11/422,190 →
Packets Transfer Device That Intelligently Accounts for Variable Egress Channel Widths When Scheduling Use of Dispatch Bus by Egressing Packet Streams
Efficient Strip-Down and Re-Alignment of Ingressing Physical Layer/Data Layer Packets in an Aggregated Pci-Express Port Having Eight Lanes
Method of Improving Over Protocol-Required Scheduling Tables While Maintaining Same
Device and Method for Handling Catastrophic Routing
Patent:
7,756,014 →
Application:
11/677,697 →
Variably Delayable Transmission of Packets Between Independently Clocked Source, Intermediate, and Destination Circuits While Maintaining Orderly and Timely Processing in One or Both of the Intermediate and Destination Circuits
Integrated Memory for Storing Egressing Packet Data, Replay Data and to-Be Egressed Data
Programmably Sliceable Switch-Fabric Unit and Methods of Use
Integrated Memory for Storing Egressing Packet Data, Replay Data and to-Be Egressed Data
Method and Apparatus for Conversion of an Arbitration Table into Count Values to Control the Distribution of Resources
Patent:
7,787,378 →
Application:
11/854,495 →
Method of Skipping Nullified Packets During Mass Replay from Replay Buffer
System and Method for Deskewing Data Transmitted Through Data Lanes
Patent:
7,995,696 →
Application:
12/188,195 →
Method of Tracking Arrival Order of Packets into Plural Queues
Multi-Queue System and Method for Deskewing Symbols in Data Streams
Patent:
8,161,210 →
Application:
12/264,158 →
Data Aggregation System and Method for Deskewing Data at Selectable Data Rates
Patent:
8,285,884 →
Application:
12/264,184 →
Congestion Management for a Packet Switch
Patent:
8,174,969 →
Application:
12/625,491 →
High-Performance Ingress Buffer for a Packet Switch
Patent:
8,391,302 →
Application:
12/630,811 →
Predictive Flow Control for a Packet Switch
Patent:
8,295,293 →
Application:
12/639,938 →
Packet Switch with Enqueue Structure for Ordering Packets
Patent:
8,284,790 →
Application:
12/701,472 →
Pipeline Scheduler for a Packet Switch
Patent:
8,400,915 →
Application:
12/710,592 →
Pci Express Switch and Method for Multi-Port Non-Transparent Switching
Patent:
8,429,325 →
Application:
12/852,399 →
System and Method for Generating Locator Polynomials
Patent:
8,327,243 →
Application:
12/857,391 →
Bch Data Correction System and Method
Patent:
8,397,144 →
Application:
12/913,716 →
Nonvolatile Memory Controller with Two-Stage Error Correction Technique for Enhanced Reliability
Patent:
8,707,122 →
Application:
13/023,336 →
Nonvolatile Memory Controller with Host Controller Interface for Retrieving and Dispatching Nonvolatile Memory Commands in a Distributed Manner
Patent:
8,588,228 →
Application:
13/052,008 →
Interrupt Technique for a Nonvolatile Memory Controller
Patent:
8,554,968 →
Application:
13/052,388 →
System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique
Patent:
8,601,346 →
Application:
13/052,835 →
System and Method for Routing a Data Message Through a Message Network
Patent:
8,656,071 →
Application:
13/107,265 →
Data Regeneration Apparatus and Method for Pci Express
Patent:
8,599,913 →
Application:
13/195,685 →
Error Correction Code Technique for Improving Read Stress Endurance
Patent:
8,694,855 →
Application:
13/287,443 →
Shuffler Error Correction Code System and Method
Patent:
8,694,849 →
Application:
13/330,573 →
Nonvolatile Memory Controller with Concatenated Error Correction Codes
Patent:
8,656,257 →
Application:
13/434,770 →
Nonvolatile Memory Controller with Error Detection for Concatenated Error Correction Codes
Patent:
8,621,318 →
Application:
13/435,572 →
Method and Apparatus for an Aggregated Non-Transparent Requester Id Translation for a Pcie Switch
Patent:
8,917,734 →
Application:
13/681,257 →
Flexible Routing Engine for a Pci Express Switch and Method of Use
Patent:
9,025,495 →
Application:
13/743,225 →
Method and Apparatus for Translated Routing in an Interconnect Switch
Patent:
8,995,302 →
Application:
13/743,281 →
Method and Apparatus for Mapped I/O Routing in an Interconnect Switch
Patent:
9,146,890 →
Application:
13/750,991 →
Apparatus and Method for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System Using Strong Log-Likelihood (Llr) Values
Patent:
9,128,858 →
Application:
13/752,757 →
Apparatus and Method Based on Ldpc Codes for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System
Patent:
9,092,353 →
Application:
13/752,885 →
Layer Specific Attenuation Factor Ldpc Decoder
Patent:
8,990,661 →
Application:
13/785,848 →
System and Method for Lifetime Specific Ldpc Decoding
Patent:
9,397,701 →
Application:
13/792,831 →
System and Method for Adaptive Check Node Approximation in Ldpc Decoding
Patent:
8,935,598 →
Application:
13/797,444 →
System and Method for Reduced Memory Storage in Ldpc Decoding
Patent:
8,984,365 →
Application:
13/860,300 →
System and Method for Avoiding Error Mechanisms in Layered Iterative Decoding
Patent:
8,984,376 →
Application:
13/860,411 →
High Performance Bch Error Correction Circuits
Application:
61/374,216 →
Non Volatile Memory Host Controller Interface Device
Application:
61/374,242 →
Error Correction Control Architecture for Reliable SSD
Application:
61/585,627 →
System and Method for Avoiding Error Mechanisms in Layered Iterative Decoding
Application:
61/781,873 →
System and Method for Ldpc Decoding Having Reduced Memory Storage Requirements
Application:
61/782,263 →
Additive-White-Gaussian_Noise Generation on an FPGA or ASIC
Application:
61/792,124 →
Optimal Threshold Placement for LDPC
Application:
61/792,591 →
System and Method for Higher Quality Log Likelihood Ratios in Ldpc Decoding
Application:
61/793,198 →
System and Method for Accumulating Soft Information in Ldpc Decoding
Application:
61/794,750 →
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Corrective Assignment to Correct the Conveying and Receiving Parties Previously Recorded on Reel 030832 Frame 0604. Assignor(S) Hereby Confirms the Conveying Party Data: Integrated Device Technology, Inc. Teceiving: Pmc-Sierra Us, Inc.
Jul 23, 2013
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: PMC-SIERRA US, INC.
Reel/Frame 030919/0040 →
Security Interest in Patents
Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
Release of Security Interest
Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
Patent Security Agreement
Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
Assignment of Assignor's Interest
Mar 17, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (US), INC.
Reel/Frame 038016/0493 →
Release of Security Interest
May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →