Granted Patent B1

US 7,694,025 · App. 11/395,918 · Granted Apr 6, 2010

Abstract

Claims (40)

1. A base address sorting device to create a sorted array of base address registers in which a target base address can be identified, for use in a serial switch, comprising:

an array of shadow registers, each shadow register in said array of shadow registers being electrically coupled to a base address register of an array of base address registers, each of said base address registers containing a base address, wherein each of the base addresses contained in said base address registers designates an identifying address of a specific external device; and

control logic circuitry electrically coupled to said array of shadow registers and said array of base address registers, said control logic circuitry operable upon receiving a configuration command comprising a new base address to implement a method for reconfiguring the contents of said array of base address registers, said method comprising:

inserting said new base address of said configuration command into a shadow register in said array of shadow registers;

sorting said array of shadow registers, including the shadow register having the new base address, into either an ascending or a descending order based on the base address of the shadow register, wherein the order of the shadow registers determines the order in which a search for the target base address in the array of base address registers will be performed; and

copying said sorted contents of said array of shadow registers into said array of base address registers.

2. The base address sorting device of claim 1 further comprising a comparator and a buffer for storing a new base address contained in said configuration command, said comparator being electrically coupled to said array of shadow registers and to said buffer and operable to compare a base address contained by a first shadow register of said array of shadow registers to said new base address held by said configuration command.

3. The base address sorting device of claim 1 wherein said control logic circuitry is operable to sort said array of shadow registers by shifting the contents of said array of shadow registers until the array of shadow registers are sorted into either the ascending or the descending order based on the base address of the shadow register.

4. The base address sorting device of claim 1 wherein said array of shadow registers further comprises a first multiplexer and a second multiplexer electrically coupled to said array of shadow registers, said logic control circuitry, and to said array of base address registers.

5. The base address sorting device of claim 1 wherein said array of shadow registers is electrically coupled so as to be able to copy said contents of each shadow register in said array of shadow registers to another shadow register in said array and to each corresponding base address register in said array of base address registers.

6. The base address sorting device of claim 1 wherein inserting said new base address of said configuration command into a shadow register in said array of shadow registers further comprises:

comparing a base address of a top shadow register to that of said new base address, and if the new base address is greater than the base address of the top shadow register, swapping the new base address with the base address of the top shadow register, or if the new base address is not greater than the base address of the top shadow register, unidirectionally rotating the array of shadow registers one logical position and comparing the base address of the top shadow register to that of the new base address and continuing the steps of unidirectionally rotating the array and comparing the base address of the top shadow register to that of the new base address until the new base address is greater than the base address of the top shadow register and then swapping the new base address with the base address of the top shadow register;

rotating said array of shadow registers back to either the ascending or descending order; and

copying said base address values of said array of shadow registers to those of said array of base address registers.

7. A switching device for switching a communication packet, comprising:

a plurality of communication ports, each of said plurality of communication ports coupled to an external electronic device;

a base address sorting device for creating a sorted array of base address registers in which a target base address can be identified, the base address sorting device comprising an array of shadow registers, each shadow register in said array of shadow registers being electrically coupled to a base address register of an array of base address registers, each of said base address registers containing a base address, wherein each of the base addresses contained in said base address registers designates an identifying address of a specific external device;

control logic circuitry electrically coupled to said array of shadow registers and said array of base address registers, said control logic circuitry operable upon receiving a configuration command comprising a new base address to implement a method for reconfiguring the contents of said array of base address registers, said method comprising:

inserting said new base address of said configuration command into a shadow register in said array of shadow registers;

sorting said array of shadow registers, including the shadow register having the new base address, into either an ascending or a descending order based on the base address of the shadow register, wherein the order of the shadow registers determines the order in which a search for the target base address in the array of base address registers will be performed; and

copying said sorted contents of said array of shadow registers into said array of base address registers; and

a switch core electronically coupled to each of said communication ports, the switch core enabled to direct the routing of said communication packet to an external device associated with the communication port.

8. The switching device described in claim 7 , wherein said communication packet is a PCI Express packet.

9. The switching device described in claim 7 , wherein each base address register contains a base address and a port name, said array of base address registers having the base addresses and associated port names for all of said communication ports in said switching device.

10. The switching device described in claim 7 , further comprising:

a renaming device electronically coupled to said base address sorting device and enabled to rename a port name in a shadow register; and

an invalidation circuit for invalidating an old base address when said old base address is replaced by inserted new base address.

11. The switching device described in claim 7 wherein each of said shadow registers in said array of shadow registers is electronically coupled to an adjacent shadow register so as to enable the contents of each of said shadow registers to be shifted to said adjacent shadow register.

12. The switching device described in claim 7 wherein said array of shadow registers further comprises a comparator electronically coupled between a shadow register in said array of shadow registers and an address buffer, said comparator operable to compare a base address in said first shadow resister to a base address in said buffer.

13. The switching device described in claim 7 wherein said switching device is a serial switch.

14. In a switching device, a method for reconfiguring a base address in an array of base address registers, said array of base address registers sorted into either an ascending or a descending order, wherein the order of the base address registers determines the order in which a search for a target base address in the array of base address registers will be performed, comprising:

receiving a configuration command comprising a new base address;

comparing the base address of a top shadow register in the array of base address registers to that of said new base address, and if the new base address is greater than the base address of the top shadow register, swapping the new base address with the base address of the top shadow register, or if the new base address is not greater than the base address of the top shadow register, unidirectionally rotating the array of shadow registers one logical position and comparing the base address of the top shadow register to that of the new base address and continuing the steps of unidirectionally rotating the array and comparing the base address of the top shadow register to that of the new base address until the new base address is greater than the base address of the top shadow register and then swapping the new base address with the base address of the top shadow register;

invalidating said old base address when the port name associated with said old base address is the same as the port name associated with said new base address;

rotating said array of shadow registers back to the ascending or the descending order; and

copying said contents of said array of shadow registers into said array of base address registers.

15. The method described in claim 14 further comprising comparing said new base address of said configuration command to the address range of the upstream port in said switching device and, if said new base address of said configuration command is greater than said address range, sending said configuration command back to a root complex as an unsupported request.

16. The method described in claim 14 wherein said copying said contents of said array of shadow registers into said array of base address registers is completed in one clock cycle.

17. The method described in claim 14 wherein each shadow register in said array of shadow registers initially contains content identical to that of a corresponding base address register in said array of base address registers.

18. The method described in claim 14 wherein said switching device is implemented in a system conforming to PCI Express standards.

Assignments (8)