Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system
View Patent ↗Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.
1. A system for correcting errors in data read from memory cells, comprising:
a memory controller, the memory controller has an encoder, and a decoder, the memory controller is configured to adjust a correctable raw bit error rate limit in response to different bit error rates occurring in data read from the memory cells; wherein the correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, and is subsequently adjusted by changing a number of soft bits allocated for message values during soft-decision decoding or changing a code-rate of a structured code.
2. The system of claim 1 , wherein the code-rate is changed by virtually bypassing a portion of the encoder and a portion of the decoder.
3. The system of claim 2 , wherein the portion is equal to a multiple of a processing engine width.
4. The system of 3 , further comprising:
setting a log-likelihood ratio (LLR) for a number of bits in the encoder to a strong value.
5. The system of claim 4 , wherein the strong LLR value for the bits set in the encoder is selected from the group consisting of a value that is strongly resistant to change, a value that is fixed during the encoding, and a guard value.
6. The system of claim 1 , wherein the code-rate is changed by virtually disabling a portion of the encoder and the decoder.
7. The system of claim 1 , wherein the structured code is selected from the group consisting of a low density parity check code (LDPC), a quasi-cyclic low density parity check code (QC-LDPC), an irregular repeat-accumulate (IRA) code, a code from projective geometry, and a user defined quasi-cyclic code.
8. A method for correcting errors in data read from memory cells, comprising:
decoding data at a first time with a decoder, the decoding corrects errors in data read from the memory cells up to a first correctable raw bit error rate limit; and
adjusting the decoding at a subsequent time, the adjusting enables the decoding to correct errors in data read from the memory cells up to a second correctable raw bit error rate limit; wherein the decoder is configured from a single decode matrix and the decoder is configured to be switched from hard-decision decoding to soft-decision decoding and a number of soft bits is dynamically allocated for soft-decision decoding on the fly which enables the decoder to correct errors occurring in data read from the memory cells at different correctable raw bit error rate limits.
9. The method of claim 8 , wherein the decoding was performed with soft-decision decoding at a first code-rate and the adjusting changes the decoding to soft-decision decoding at a second code-rate.