Device and method for address matching with post matching limit check and nullification
View Patent ↗A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a data selector circuit that is enabled to select the content of an address register in an array of address registers, and a comparator electrically coupled to the data selector circuit and enabled to take a first input from the data selector circuit and target address as a second input from a communication packet. The method includes receiving the target address, seeking and locating a matching address in an array of base address registers, directing the packet to the port associated with the matching address, determining the target address to be a valid address by comparing the target address with a limit address associated with the matching base address, and nullifying the match if the target address is greater than the limit address.
1. A limit address check validation device in a communication packet switching device, the communication packet switching device comprising a switch core and an array of base address registers, each base address register in the array of base address registers comprising a base address, a limit address and a port identifier and the communication packet comprising a target address indicating a port, the limit address check validation device comprising:
a data selector circuit to select a limit address associated with a matching base address register in the array of base address registers; and
a comparator electrically coupled to the data selector circuit, the comparator to compare the target address of the communication packet to the selected limit address to determine if the target address is a valid address, the comparison performed after the communication packet has been routed to the port identifier of the switch core associated with the matching base address register, and upon comparison, if it is determined that the target address of the communication packet is not a valid address, the comparator to nullify the routing of the communication packet.
2. The limit address check validation device described in claim 1 , further comprising a buffer for storing the limit address contained in the matching base address register wherein the buffer is electrically coupled to the array of base address registers.
3. The limit address check validation device described in claim 1 , wherein the data selector circuit is a multiplexer.
4. The limit address check validation device described in claim 1 , wherein the base address registers in the array of base address registers are sorted in a descending order.
5. The limit address check validation device described in claim 4 , wherein, the matching base address register is identified as the largest base address that is less than or equal to the target address of the communication packet.
6. The limit address check validation device described in claim 1 , wherein the data selector circuit selects the limit address based on the matching base address register output provided by an address matching device in the switching device.
7. The limit address check validation device described in claim 1 , wherein the data selector circuit receives an input from each of the base address registers in the array of base address registers.
8. The limit address check validation device described in claim 1 , wherein the communication packet is routed to the port associated with the matching base address register by routing the port identifier associated with the matching base address register to the switch core.
9. The limit address check validation device described in claim 1 , wherein it is determined that the target address of the communication packet is not a valid address when the target address is determined to be greater than the limit address associated with the matching base address register.
10. A switching device for switching a communication packet, comprising:
a switch core enabled to direct the routing of the communication packet;
a plurality of communication ports, each of the communication ports electronically coupled to the switch core and to an external electronic device, each of the ports associated with a base address and a limit address and a port identifier;
an array of base address registers, wherein content in the array of base address registers includes the base address and the limit address and the port identifier;
a base address matching logic circuit to select a matching base address register in the array of base address registers and to route the communication packet to the port identified by the port identifier associated with the matching base address register;
a limit check validation circuit for comparing a selected limit address associated with the matching base address selected by the base address matching logic circuit to a target address in the communication packet, said limit check validation circuit to compare the target address to the selected limit address to determine if the target address is a valid address, the comparison performed after the communication packet has been routed to the port identified by the port identifier associated with the matching base register, and upon comparison, if it is determined that the target address of the communication packet is not a valid address, the limit check validation circuit to nullify the routing of the communication packet.
11. The switching device described in claim 10 , wherein the limit check validation circuit is enabled to transmit a nullify signal to the switch core if the target address is greater than the selected limit address.
12. The switching device described in claim 10 , wherein the communication packet is a PCI Express packet.
13. The switching device described in claim 10 wherein the switching device is a serial switch.
14. In a switching device, a method for address matching, comprising:
receiving a target address in a communication packet;
seeking a matching address from a set of sorted base addresses in an array of base address registers, each base address register associated with a port in the switching device;
locating the matching address in the array of base address registers;
directing the communication packet to a port associated with the matching address;
determining whether the target address is a valid address after the communication packet has been directed to the port associated with the matching address; and
nullifying the directing of the communication packet if the target address is not a valid address.
15. The method for address matching described in claim 14 , wherein locating the matching address in the array of base address registers comprises selecting the numerically largest base address, in the set of sorted base addresses, that is numerically less than or equal to the target address.
16. The method for address matching described in claim 14 , wherein determining whether the target address is a valid address comprises comparing the target address in the communication packet with the selected limit address associated with the matching address.
17. The method for address matching described in claim 14 wherein the switching device is implemented in a system conforming to PCI Express standards.
18. The switching device described in claim 10 , wherein it is determined that the target address of the communication packet is not a valid address when the target address of the communication packet is determined to be greater than the selected limit address associated with the matching base address register.