System and method for generating parity data in a nonvolatile memory controller by using a distributed processing technique
View Patent ↗A nonvolatile memory controller performs a data stripe operation on data blocks by processing a collection of commands. The nonvolatile memory controller includes command processing units, each of which processes a command of the data stripe operation to store a data block into a nonvolatile memory device. A parity calculator in the nonvolatile memory controller receives the data blocks of the data stripe operation by receiving a sequence of data blocks. The parity calculator generates a parity block in a page frame as the parity calculator receives the sequence of the data blocks. A command processing unit in the nonvolatile memory controller determines when the parity calculator has completed generating the parity block and writes the parity block to a nonvolatile memory device.
1. A nonvolatile memory controller for performing a data stripe operation on a plurality of data blocks, the nonvolatile memory controller comprising:
a plurality of command processing units, each command processing unit of the plurality of command processing units configured to receive a command of a plurality of commands for performing the data stripe operation, the plurality of commands including a plurality of data update commands and a parity write command, each command processing unit of the plurality of command processing units receiving a data update command of the plurality of data update commands configured to request a data block of the plurality of data blocks based on the data update command, receive the data block in response to the request, and write the data block to a nonvolatile memory device; and
a parity calculator coupled to the plurality of command processing units, the parity calculator further comprising a context memory including a page frame, the parity calculator configured to receive the plurality of data blocks as a sequence of data blocks, to generate a parity block by storing a first data block of the sequence of data blocks into the page frame and updating the data block stored in the page frame with each data block following the first data block in the sequence of data blocks, without storing each data block in a data buffer, the command processing unit receiving the parity write command configured to write the parity block to a nonvolatile memory based on the parity write command.
2. The nonvolatile memory controller of claim 1 , wherein the parity calculator is further configured to update the data block stored in the page frame by performing a logical operation on the data block stored in the page frame and a data block following the first data block in the sequence of data blocks.
3. The nonvolatile memory controller of claim 2 , wherein the logical operation includes an exclusive-or operation.
4. The nonvolatile memory controller of claim 1 , further comprising a context associated with the page frame and including a stripe count for counting each occurrence of updating the parity block, the nonvolatile memory controller further comprising a command distribution unit configured to determine the parity block is generated by determining the stripe count has reached a threshold value.
5. The nonvolatile memory controller of claim 1 , wherein the nonvolatile memory controller further comprises a command distribution unit configured to distribute the plurality of data update commands to command processing units of the plurality of command processing units, determine generation of the parity block is complete, and distribute the parity write command to a command processing unit of the plurality of command processing units in response to determining the parity block is complete.
6. The nonvolatile memory controller of claim 1 , further comprising:
a controller memory configured to store the plurality of data blocks; and
a data network coupled to the controller memory, the plurality of command processing units, and the parity calculator, wherein the plurality of command processing units is further configured to request the plurality of data blocks by generating a plurality of data request packets, the controller memory is further configured to generate a plurality of completion packets including the plurality of data blocks, and both the parity calculator and the plurality of command processing units are further configured to receive the plurality of data blocks through the data network.
7. The nonvolatile memory controller of claim 6 , wherein the nonvolatile memory controller further comprises a command distribution unit configured to distribute the plurality of data update commands to command processing units of the plurality of command processing units, determine generation of the parity block is complete, and distribute the parity write command to a command processing unit of the plurality of command processing units in response to determining the parity block is complete.
8. The nonvolatile memory controller of claim 7 , wherein each command processing unit of the plurality of command processing units comprises a command processing unit command queue for storing commands distributed to the command processing unit from the command distribution unit.
9. The nonvolatile memory controller of claim 7 , further comprising a context memory including a plurality of page frames, wherein each command of the plurality of commands includes a flow identifier, and the command distribution unit is further configured to allocate a page frame of the context memory to the data stripe operation by associating the flow identifier with the page frame.
10. The nonvolatile memory controller of claim 1 , wherein the plurality of command processing units is further configured to perform a plurality of data stripe operations in parallel.
11. A nonvolatile memory controller comprising:
a command distribution unit configured to receive a plurality of commands for performing a data stripe operation on a plurality of data blocks, the plurality of commands comprising a plurality of data update commands and a parity write command;
a plurality of command processing units coupled to the command distribution unit, the command distribution unit further configured to distribute the plurality of data update commands among command processing units of the plurality of command processing units, each command processing unit receiving a data update command configured to request a data block of the plurality of data blocks based on the data update command, receive the data block in response to the request, and write the data block to a nonvolatile memory device; and
a parity calculator coupled to the plurality of command processing units, the parity calculator including a context memory including a page frame, the parity calculator configured to receive the data blocks of the plurality of data blocks as a sequence of data blocks, to generate a parity block by storing a first data block of the sequence of data blocks into the page frame and updating the data block stored in the page frame by performing an exclusive-or operation on the data block stored in the page frame and a data block following the first data block in the sequence of data blocks, the command distribution unit further configured to determine generation of the parity block is complete and to distribute the parity write command to a command processing unit of the plurality of command processing units in response to determining the parity block is complete, the command processing unit receiving the parity write command configured to write the parity block into the nonvolatile memory device.
12. The nonvolatile memory controller of claim 11 , wherein the plurality of command processing units is further configured to process the plurality of data update commands in an arbitrary order.
13. The nonvolatile memory controller of claim 12 , wherein the context memory includes a plurality of page frames for storing a plurality of parity blocks of a plurality of data stripe operations, and wherein the plurality of command processing units is further configured to perform the plurality of data stripe operations in parallel.
14. A method of generating parity data, the method comprising:
distributing a plurality of commands for performing the data stripe operation among a plurality of command processing units in the nonvolatile memory controller, the plurality of commands including a plurality of data update commands and a parity write command;
generating a plurality of data requests by the plurality of command processing units based on the plurality of data update commands;
receiving a plurality of data blocks at the plurality of command processing units and at a parity calculator of the nonvolatile memory controller in response to the plurality of data requests;
writing the plurality of data blocks to a plurality of nonvolatile memory devices by the plurality of command processing units;
generating a parity block in a page frame of a context memory by the parity calculator based on the plurality of data blocks by initializing a parity block in the page frame by storing a first data block of the sequence of data blocks into the page frame and updating the data block stored in the page frame with each data block following the first data block in the sequence of data blocks, without storing each data block in a data buffer;
determining that generation of the parity block is complete; and
writing the parity block to a nonvolatile memory device by a command processing unit of the plurality of command processing units based on the parity write command after determining generation of the parity block is complete.
15. The method of claim 14 , wherein updating the data block stored in the page frame with each data block following the first data block in the sequence of data blocks comprises performing an operation on the data block stored in the page frame and a data block following the first data block in the sequence of data blocks.
16. The method of claim 15 , wherein the operation includes an exclusive-or operation.
17. The method of claim 14 , further comprising:
initializing a stripe count to a predetermined value; and
decrementing the stripe count in response to each occurrence of updating the parity block, wherein determining generation of the parity block is complete comprises determining the stripe count has reached a threshold value.
18. The method of claim 14 , wherein the context memory includes a plurality of page frames and each command of the plurality of commands includes a flow identifier, the method further comprising allocating a page frame in the context memory to the data stripe operation by associating the flow identifier with the page frame.