System and method for higher quality log likelihood ratios in LDPC decoding
A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.
1. A method of providing one or more log likelihood ratio (LLRs) of a target cell to a low-density parity check (LDPC) decoder, the method comprising:
storing a neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module, the neighboring cell contribution LLR look-up table including combinations of possible read patterns for the target cell and the neighboring cells, and associated LLR's, each of the LLR's corresponding to a bit error rate for the associated possible read pattern;
reading a threshold voltage of a target cell stored in a nonvolatile memory storage module;
reading a threshold voltage of one or more neighboring cells of the target cell stored in the nonvolatile memory storage module;
accessing the neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module;
extracting from the neighboring cell contribution LLR look-up table the LLR corresponding to the pattern of the read of the threshold voltage of the target cell and the read of the threshold voltage of the one or more neighboring cells; and
providing the extracted LLR to an LDPC decoder.
2. The method of claim 1 , wherein reading a threshold voltage of a target cell stored in a nonvolatile memory storage module further comprises, reading the threshold voltages of a logical page of cells of the nonvolatile memory storage module, the logical page of cells including the target cell.
3. The method of claim 1 , wherein reading a threshold voltage of one or more neighboring cells of the target cell stored in the nonvolatile memory storage module further comprises, reading the threshold voltages of one or more logical pages of cells of the nonvolatile memory storage module, each of the one or more logical pages including one of the neighboring cells.
4. The method of claim 1 , wherein reading a threshold voltage of a target cell stored in a nonvolatile memory storage module further comprises, using a plurality of soft-decision reference voltages to read a plurality of threshold voltages of the target cell.
5. The method of claim 1 , wherein reading a threshold voltage of one or more neighboring cells of the target cell stored in a nonvolatile memory storage module further comprises, using a plurality of soft-decision reference voltages to read a plurality of threshold voltages of each of the one or more neighboring cells.
6. The method of claim 1 , wherein accessing the neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module further comprises accessing a neighboring cell contribution LLR look-up table associated with a current point in the lifetime of the nonvolatile memory storage module.
7. The method of claim 1 , wherein accessing the neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module further comprises accessing a neighboring cell contribution LLR look-up table associated with a logical page of the nonvolatile memory storage module that includes the target cell.
8. The method of claim 1 , wherein the nonvolatile memory storage module comprises a plurality of pages organized in an interleaved architecture or in an all-bit-line (ABL) architecture.
9. A method of providing one or more log likelihood ratio (LLRs) of a target cell to a low-density parity check (LDPC) decoder, the method comprising:
reading a threshold voltage of a target cell stored in a nonvolatile memory storage module;
reading a threshold voltage of one or more neighboring cells of the target cell stored in the nonvolatile memory storage module;
accessing a neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module, the accessing a neighboring cell contribution LLR look-up table associated with the nonvolatile memory storage module further comprising accessing a first neighboring cell contribution look-up table when the threshold voltage of the target cell indicates a programmed state of the target cell and accessing a second neighboring cell contribution look-up table when the threshold voltage of the target cell indicates an unprogrammed state of the target cell, wherein the first neighboring cell contribution look-up table is different than the second neighboring cell contribution look-up table;
extracting an LLR associated with the threshold voltage of the target cell and the threshold voltage of the one or more neighboring cells from the first neighboring cell contribution LLR look-up table or the second neighboring cell contribution LLR look-up table; and
providing the extracted LLR to an LDPC decoder.
10. A nonvolatile memory controller for providing one or more log likelihood ratios (LLRs) of a target cell for LDPC decoding, the controller comprising:
read circuitry configured for reading a threshold voltage of a target cell stored in a nonvolatile memory storage module and for reading a threshold voltage of one or more neighboring cells of the target cell stored in the nonvolatile memory storage module;
one or more neighboring cell contribution LLR look-up tables associated with the nonvolatile memory storage module, the one or more neighboring cell contribution LLR look-up tables including combinations of possible read patterns for the target cell and the neighboring cells, and associated LLR's, each of the LLR's corresponding to a bit error rate for the associated possible read pattern; and
look-up circuitry configured for extracting an LLR associated with the threshold voltage of the target cell and the threshold voltage of the one or more neighboring cells from the one or more neighboring cell contribution LLR look-up tables and for providing the extracted LLR to an LDPC decoder.
11. The controller of claim 10 , wherein the read circuitry is further configured for reading a logical page of the nonvolatile memory storage module, the logical page including the target cell.
12. The controller of claim 10 , wherein the read circuitry is further configured for reading one or more neighboring logical pages of the nonvolatile memory storage, each of the one or more neighboring logical pages including one of the neighboring cells of the target cell.
13. The controller of claim 10 , wherein the read circuitry is further configured for using a plurality of soft-decision reference voltages to read a plurality of threshold voltages of the target cell.
14. The controller of claim 10 , wherein the read circuitry is further configured for using a plurality of soft-decision reference voltages to read a plurality of threshold voltages of each of the one or more neighboring cells.
15. The controller of claim 10 , wherein the one or more neighboring cell contribution LLR look-up tables includes a neighboring cell contribution LLR look-up table that is associated with a current point in the lifetime of the nonvolatile memory storage module.
16. The controller of claim 10 , the one or more neighboring cell contribution LLR look-up tables includes a neighboring cell contribution LLR look-up table that is associated with a logical page of the nonvolatile memory storage module that includes the target cell.
17. The controller of claim 10 , wherein the nonvolatile memory storage module comprises a plurality of pages organized in an interleaved architecture or in an all-bit-line (ABL) architecture.
18. A nonvolatile memory controller for providing one or more log likelihood ratios (LLRs) of a target cell for LDPC decoding, the controller comprising:
read circuitry configured for reading a threshold voltage of a target cell stored in a nonvolatile memory storage module, and for reading a threshold voltage of one or more neighboring cells of the target cell stored in the nonvolatile memory storage module;
one or more neighboring cell contribution LLR look-up tables associated with the nonvolatile memory storage module, including a first neighboring cell contribution look-up table associated with a programmed state of the target cell and a second neighboring cell contribution look-up table associated with an unprogrammed state of the target cell, wherein the first neighboring cell contribution look-up table is different than the second neighboring cell contribution look-up table; and
look-up circuitry configured for extracting an LLR associated with the threshold voltage of the target cell and the threshold voltage of the one or more neighboring cells from the one or more neighboring cell contribution LLR look-up tables and for providing the extracted LLR to an LDPC decoder.