Systems and methods for signature circuits
View Patent ↗Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.
1. A signature circuit comprising:
a first check symbol generator circuit in communication with a circuit under test (CUT), where the first check symbol generator circuit is configured to generate a first error detection code that is a parity type of code as an output; and
a second check symbol generator circuit in communication with the first check symbol generator circuit, wherein the second check symbol generator circuit is configured to generate a second error detection code that is a check of the first error detection code from states of at least a portion of the first error detection code as the first error detection code is being generated, wherein the second check symbol generator circuit is configured to generate a weight-based code of an information word from the first check symbol generator circuit such that the second error detection code is a different type of error detection code than the first error detection code.
2. The signature circuit as defined in claim 1 , wherein the first check symbol generator circuit corresponds to a diagonal bit-interleaved parity (BIP) check symbol generation circuit and where the second check symbol generator circuit corresponds to a Bose-Lin check symbol code generator circuit.
3. The signature circuit as defined in claim 1 , wherein the second check symbol generator circuit is further configured to generate a modulo count of logical ones or zeroes of states of an information word from the first check symbol generator circuit.
4. The signature circuit as defined in claim 1 , wherein the first check symbol generator circuit corresponds to a Multiple Input Signature Register (MISR) circuit and where the second check symbol generator circuit is configured to generate a modulo count of logical ones or zeroes of states of an information word from the MISR circuit.
5. A method of testing a circuit, the method comprising:
applying test vectors to the circuit under test;
monitoring selected signals of the circuit under test;
generating a first error detection code at least partially based on the monitored signals, wherein the first error detection code corresponds to a parity of error detection code; and
generating a second error detection code as a check for the first error detection code from states of at least a portion of the first error detection code as the first error detection code is being generated, wherein the second error detection code corresponds to a weight-based code such that the second error detection code is a different type of error detection code than the first error detection code.
6. The method as defined in claim 5 , wherein the first error detection code is generated by bit-interleaved parity and where the second error detection code corresponds to a Bose-Lin code.
7. The method as defined in claim 5 , wherein the second error detection code corresponds to a modulo count of logical ones or zeroes.
8. The method as defined in claim 5 , wherein the first error detection code corresponds to a parity type of error detection code computed by a Multiple Input Signature Register (MISR) and wherein the second error detection code corresponds to a modulo count of logical ones or zeroes.
9. A method of testing a circuit, the method comprising:
applying test vectors to the circuit under test;
monitoring selected signals of the circuit under test;
generating a first error detection code based at least partly on a parity check calculation of the monitored signals; and
generating a second error detection code as a check for the first error detection code from states of a selected bit of the first error detection code, wherein the second error detection code is a weight-based code generated by counting occurrences of one of logical “0” or “1” in the selected bit of the first error detection code as the first error detection code is being generated.
10. The method as defined in claim 9 , further comprising counting occurrences in a selected bit of a prior state of the error detection code.
11. A signature circuit comprising:
a means for monitoring selected signals of a circuit under test;
a means for generating a first error detection code at least partially based on the monitored signals, wherein the means for generating the first error detection code is configured to generate a parity type of code; and
a means for generating a second error detection code as a check for the first error detection code from states of at least a portion of the first error detection code as the first error detection code is being generated, wherein the means for generating the second error detection code is configured to generate a weight-based code such that the second error detection code is a different type of error detection code than the first error detection code.