Active biasing in metal oxide semiconductor (MOS) differential pairs
View Patent ↗Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.
1. A biasing circuit for a differential driver, the biasing circuit comprising:
a pre-driver circuit configured to generate a differential output signal, wherein each portion of the differential output signal is intended to be operatively coupled to gates of first and second source-coupled transistors of the differential driver, wherein each portion of the differential output signal has a single-ended voltage swing from a first voltage level to a second voltage level for inactivating and for activating, respectively, the transistors of the differential driver, wherein the pre-driver circuit is configured to receive an adjustment signal as a reference input for the second voltage level; and
a feedback circuit operatively coupled to a sense signal as a first input and to a voltage reference as a second input, wherein the feedback circuit is configured to manipulate the adjustment signal such that the first input and the second input at least approximately match with respect to voltage and such that the second voltage level is adjusted to bias the activated transistor of the differential driver to a saturation region and not to a triode or linear region;
wherein the sense signal corresponds to a voltage at a source node of the first and second source-coupled transistors;
wherein the differential driver further includes a third transistor coupled to the sources of the first and second transistors as a current sink or current source, the biasing circuit further comprising: a fourth transistor and a resistor wherein a drain terminal of the fourth transistor is operatively coupled to a first terminal of the resistor, and a second terminal of the resistor is operatively coupled to the voltage reference such that the voltage reference at least partially tracks changes in the saturation voltage V DSAT of the third transistor.
2. The biasing circuit as defined in claim 1 , wherein the biasing circuit and the differential driver are embodied in an integrated circuit.
3. The biasing circuit as defined in claim 1 , wherein the biasing circuit and the differential driver are embodied in a serializer/deserializer (SerDes).
4. The biasing circuit as defined in claim 1 , wherein a gate voltage bias for the third transistor and a gate voltage bias for the fourth transistor are at the same electric potential.
5. A biasing circuit for a differential driver, the biasing circuit comprising:
a pre-driver circuit configured to generate a differential output signal, wherein each portion of the differential output signal is intended to be operatively coupled to gates of first and second source-coupled transistors of the differential driver, wherein each portion of the differential output signal has a single-ended voltage swing from a first voltage level to a second voltage level for inactivating and for activating, respectively, the transistors of the differential driver, wherein the pre-driver circuit is configured to receive an adjustment signal as a reference input for the second voltage level;
a feedback circuit operatively coupled to a sense signal as a first input and to a voltage reference as a second input, wherein the feedback circuit is configured to manipulate the adjustment signal such that the first input and the second input at least approximately match with respect to voltage and such that the second voltage level is adjusted to bias the activated transistor of the differential driver to a saturation region and not to a triode or linear region;
a replica of at least a portion of the pre-driver circuit; and
a replica transistor and a replica load of at least one of the first or the second source-coupled transistors of the differential driver and applicable load, wherein the sense signal corresponds to a source voltage of the replica transistor, and wherein the adjustment signal is further operatively coupled to the replica of the pre-driver circuit such that a feedback loop is closed around the replica of the pre-driver circuit and the replica transistor.
6. The biasing circuit as defined in claim 5 , wherein the replica transistor is half of a differential pair including a second replica transistor, wherein the second replica transistor is biased in the cutoff region by the replica of the pre-driver circuit, further comprising operatively coupling a replica load to the first and the second transistors of the differential driver.
7. The biasing circuit as defined in claim 5 , wherein the biasing circuit and the differential driver are embodied in an integrated circuit.
8. The biasing circuit as defined in claim 5 , wherein the biasing circuit and the differential driver are embodied in a serializer/deserializer (SerDes).
9. A biasing circuit for a differential driver, the biasing circuit comprising:
a pre-driver circuit configured to generate a differential output signal, wherein each portion of the differential output signal is intended to be operatively coupled to gates of first and second source-coupled transistors of the differential driver, wherein each portion of the differential output signal has a single-ended voltage swing from a first voltage level to a second voltage level for inactivating and for activating, respectively, the transistors of the differential driver, wherein the pre-driver circuit is configured to receive an adjustment signal as a reference input for the second voltage level;
a feedback circuit operatively coupled to a sense signal as a first input and to a voltage reference as a second input, wherein the feedback circuit is configured to manipulate the adjustment signal such that the first input and the second input at least approximately match with respect to voltage and such that the second voltage level is adjusted to bias the activated transistor of the differential driver to a saturation region and not to a triode or linear region;
a replica of at least a portion of the pre-driver circuit; and
a replica transistor and a replica load of at least one of the first or the second source-coupled transistors of the differential driver and applicable load, wherein the sense signal corresponds to a drain voltage of the replica transistor, and wherein the adjustment signal is further operatively coupled to the replica of the pre-driver circuit such that a feedback loop is closed around the replica of the pre-driver circuit and the replica transistor.
10. The biasing circuit as defined in claim 9 , wherein the replica transistor is half of a differential pair including a second replica transistor, wherein the second replica transistor is biased in the cutoff region by the replica of the pre-driver circuit, further comprising operatively coupling a replica load to the first and the second transistors of the differential driver.
11. The biasing circuit as defined in claim 9 , further comprising a transistor for generating the voltage reference, wherein the transistor is biased by a current source to operate at or slightly below threshold, wherein a source voltage of the transistor corresponds to the voltage reference.
12. The biasing circuit as defined in claim 9 , wherein the biasing circuit and the differential driver are embodied in an integrated circuit.
13. The biasing circuit as defined in claim 9 , wherein the biasing circuit and the differential driver are embodied in a serializer/deserializer (SerDes).
14. A biasing circuit for a differential driver, the biasing circuit comprising:
a pre-driver circuit configured to generate a differential output signal, wherein each portion of the differential output signal is intended to be operatively coupled to gates of first and second source-coupled transistors of the differential driver, wherein each portion of the differential output signal has a single-ended voltage swing from a first voltage level to a second voltage level for inactivating and for activating, respectively, the transistors of the differential driver, wherein the pre-driver circuit is configured to receive an adjustment signal as a reference input for the second voltage level;
a feedback circuit operatively coupled to a sense signal as a first input and to a voltage reference as a second input, wherein the feedback circuit is configured to manipulate the adjustment signal such that the first input and the second input at least approximately match with respect to voltage and such that the second voltage level is adjusted to bias the activated transistor of the differential driver to a saturation region and not to a triode or linear region;
a replica of at least a portion of the pre-driver circuit; and
a replica transistor and replica load of at least one of the first or the second source-coupled transistors and applicable load of the differential driver, wherein the sense signal corresponds to a drain voltage of the replica transistor, wherein the voltage reference is at least partially based on the source voltage of the replica transistor, wherein the adjustment signal is further operatively coupled to the replica of the pre-driver circuit such that a feedback loop is closed around the replica of the pre-driver circuit and the replica transistor such that a drain-to-source voltage of the replica transistor is regulated by the feedback loop.
15. The biasing circuit as defined in claim 14 , wherein the voltage reference comprises a sum of the source voltage of the replica transistor and a voltage drop across a resistor, wherein the voltage drop is sufficient to keep the replica transistor biased in the saturation region.
16. The biasing circuit as defined in claim 14 , wherein the replica transistor is half of a differential pair including a second replica transistor, wherein the second replica transistor is biased in the cutoff region by the replica of the pre-driver circuit, further comprising operatively coupling a replica load to the first and the second transistors of the replica differential driver.
17. The biasing circuit as defined in claim 14 , wherein the biasing circuit and the differential driver are embodied in an integrated circuit.
18. The biasing circuit as defined in claim 14 , wherein the biasing circuit and the differential driver are embodied in a serializer/deserializer (SerDes).
19. A biasing circuit for a differential driver, the biasing circuit comprising:
a pre-driver circuit configured to generate a differential output signal, wherein each portion of the differential output signal is intended to be operatively coupled to gates of first and second source-coupled transistors of the differential driver, wherein each portion of the differential output signal has a single-ended voltage swing from a first voltage level to a second voltage level for inactivating and for activating, respectively, the transistors of the differential driver, wherein the pre-driver circuit is configured to receive an adjustment signal as a reference input for the second voltage level;
a feedback circuit operatively coupled to a sense signal as a first input and to a voltage reference as a second input, wherein the feedback circuit is configured to manipulate the adjustment signal such that the first input and the second input at least approximately match with respect to voltage and such that the second voltage level is adjusted to bias the activated transistor of the differential driver to a saturation region and not to a triode or linear region; and
a replica transistor circuit having a replica transistor, wherein the replica transistor circuit is configured to bias the replica transistor into the saturation region, wherein a combination of a relative scale of the replica transistor and a biasing current passing through the replica transistor is sufficient to bias the replica transistor with a substantially lower gate voltage than a gate voltage of the activated transistor of the differential pair, wherein the gate voltage of the replica transistor is coupled to the pre-driver circuit as a reference to generate, directly or indirectly, the first voltage level.
20. The biasing circuit as defined in claim 19 , wherein the biasing circuit and the differential driver are embodied in an integrated circuit.
21. The biasing circuit as defined in claim 19 , wherein the biasing circuit and the differential driver are embodied in a serializer/deserializer (SerDes).
22. A biasing circuit for a differential driver with a first transistor and a second transistor, the biasing circuit comprising:
a pre-driver circuit adapted to provide a differential drive signal to a gate of the first transistor and to a gate of the second transistor, wherein each portion of the differential drive signal is switched between a first voltage level and a second voltage level higher than the first voltage level in a complementary manner such that the transistor receiving the first voltage level is deactivated and the transistor receiving the second voltage level is activated;
electronic means for adjusting at least the second voltage level such that the activated transistor is operating in a saturation region;
means for biasing a replica transistor in the saturation region, wherein a combination of a relative amount of current passing through the replica transistor and a relative scale of the replica transistor to a biasing current used and a scale of the transistors of the differential pair biases the replica transistor with a substantially lower gate voltage; and
means for using the gate voltage from the replica transistor and a reference voltage for the second voltage level to generate a reference for the first voltage level.
23. A method of biasing a differential driver with a first transistor and a second transistor, the method comprising:
providing a differential drive signal to a gate of the first transistor and to a gate of the second transistor, wherein each portion of the differential drive signal is switched between a first voltage level and a second voltage level higher than the first voltage level in a complementary manner such that the transistor receiving the first voltage level is deactivated and the transistor receiving the second voltage level is activated;
electronically adjusting at least the second voltage level such that the activated transistor is operating in a saturation region;
regulating a drain voltage of an activated replica transistor such that the activated replica transistor is operating in the saturation region;
using an adjustment signal for the activated replica transistor as a reference voltage for the second voltage level of the differential drive; and
electronically adjusting the second voltage level by using a feedback loop to regulate a voltage at a drain terminal of the activated replica transistor, wherein the feedback loop includes a replica pre-driver circuit for the activated replica transistor but the feedback loop does not include the differential driver or the pre-driver circuit.
24. The method as defined in claim 23 , wherein electronically adjusting at least the second voltage level comprises compensating for process, voltage, and temperature (PVT) variations.
25. The method as defined in claim 23 , further comprising biasing a third transistor in the saturation region, wherein the third transistor is coupled to the sources of the first transistor and the second transistor, wherein the third transistor is used as a current sink or current source.
26. The method as defined in claim 23 , wherein the activated replica transistor is half of a replica differential pair.
27. The method as defined in claim 23 , further comprising using another replica transistor to generate a fraction of a threshold voltage as a reference for regulating the drain voltage of the activated replica transistor.
28. A method of biasing a differential driver with a first transistor and a second transistor, the method comprising:
providing a differential drive signal to a gate of the first transistor and to a gate of the second transistor, wherein each portion of the differential drive signal is switched between a first voltage level and a second voltage level higher than the first voltage level in a complementary manner such that the transistor receiving the first voltage level is deactivated and the transistor receiving the second voltage level is activated;
electronically adjusting at least the second voltage level such that the activated transistor is operating in a saturation region;
regulating a drain-to-source voltage of an activated replica transistor such that the activated replica transistor is operating in the saturation region;
using an adjustment signal for the activated replica transistor as a reference voltage for the second voltage level of the differential drive; and
electronically adjusting the second voltage level by using a feedback loop to regulate a drain-to-source voltage of the activated replica transistor, wherein the feedback loop includes a replica pre-driver circuit for the activated replica transistor but not the differential driver or the pre-driver circuit.
29. The method as defined in claim 28 , wherein the activated replica transistor is half of a replica differential pair.
30. A method of biasing a differential driver with a first transistor and a second transistor, the method comprising:
providing a differential drive signal to a gate of the first transistor and to a gate of the second transistor, wherein each portion of the differential drive signal is switched between a first voltage level and a second voltage level higher than the first voltage level in a complementary manner such that the transistor receiving the first voltage level is deactivated and the transistor receiving the second voltage level is activated;
electronically adjusting at least the second voltage level such that the activated transistor is operating in a saturation region;
biasing a replica transistor in the saturation region under similar conditions as the activated transistor; and
using a gate voltage from the replica transistor as a voltage reference for the second voltage level of the differential drive;
wherein the replica transistor is connected in a diode configuration;
wherein the diode configuration further comprises using a drain resistor in series with the drain of the replica transistor and a source resistor in series with the source of the replica transistor.
31. The method as defined in claim 30 , further comprising providing the replica transistor with drain and source voltages that are substantially the same as that experienced by the activated transistor of the differential pair.
32. A method of biasing a differential driver with a first transistor and a second transistor, the method comprising:
providing a differential drive signal to a gate of the first transistor and to a gate of the second transistor, wherein each portion of the differential drive signal is switched between a first voltage level and a second voltage level higher than the first voltage level in a complementary manner such that the transistor receiving the first voltage level is deactivated and the transistor receiving the second voltage level is activated;
electronically adjusting at least the second voltage level such that the activated transistor is operating in a saturation region;
biasing a replica transistor into the saturation region, wherein a combination of a relative amount of current passing through the replica transistor and a relative scale of the replica transistor to a biasing current used and a scale of the transistors of the differential pair biases the replica transistor with a substantially lower gate voltage than a gate voltage for the activated transistor; and
using the gate voltage from the replica transistor and a reference voltage for the second voltage level to generate a reference for the first voltage level.
33. The method as defined in claim 32 , further comprising electronically adjusting the first voltage level such that the inactivated transistor is cutoff, and such that the total voltage swing between the first voltage level and the second voltage level is minimized.
34. The method as defined in claim 32 , further comprising providing the replica transistor with drain and source voltages that are substantially the same as that experienced by the deactivated transistor of the differential pair.