Pattern-based DC offset correction
View Patent ↗DC offsets in high-gain amplifiers should be corrected to avoid the signal distortion that would result from amplifier saturation. A predominantly digital technique is described in which a digital algorithm observes patterns in the sign of the amplifier output and drives a digital-to-analog converter (DAC), which reduces the amplifier's offset.
1. A method for correcting one or more DC offsets in an amplifier, the method comprising:
slicing an output signal of a gain stage of the amplifier to generate a 1-bit sliced signal, wherein symbols of the 1-bit sliced signal comprises a first state or a second state, wherein slicing is performed by electronic hardware;
determining the presence of one or more patterns associated with DC offsets from the output signal of the gain stage of the amplifier by analyzing the 1-bit sliced signal for run length, wherein a run length comprises a count of consecutive runs of the first state or the second state, wherein a run length of at least a threshold value for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively; and
generating a correction to reduce the DC offset based at least partly on a count of the run length of the first state or the second state.
2. The method of claim 1 , wherein generating the correction comprises adjusting an output voltage of a digital to analog converter (DAC) based at least partly on one or more observed run length patterns.
3. The method of claim 1 , wherein analyzing further comprises comparing the run length to one or more fixed thresholds.
4. A method for correcting one or more DC offsets in an amplifier, the method comprising:
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier, wherein determining the presence of one or more patterns comprises:
slicing an output signal of the gain stage to generate a sliced signal; and
analyzing the sliced signal for run length, wherein analyzing further comprises comparing the run length to one or more thresholds, and varying the one or more thresholds to reduce false positive corrections;
generating a correction to reduce the DC offset based at least partly on the determination.
5. A method for correcting one or more DC offsets in an amplifier, the method comprising:
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier, wherein determining the presence of one or more patterns comprises:
slicing an output signal of the gain stage to generate a sliced signal; and
analyzing the sliced signal for run length, wherein analyzing further comprises calculating average values of run lengths for comparison to one or more thresholds;
generating a correction to reduce the DC offset based at least partly on the determination.
6. A method for correcting one or more DC offsets in an amplifier, the method comprising:
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier, wherein determining the presence of one or more patterns comprises:
slicing an output signal of the gain stage to generate a sliced signal; and
analyzing the sliced signal for run length, wherein analyzing further comprises calculating integrated values of run lengths and using both integrated values and instantaneous run length values for comparison to one or more thresholds;
generating a correction to reduce the DC offset based at least partly on the determination.
7. A method for correcting one or more DC offsets in an amplifier, the method comprising:
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier, wherein determining the presence of one or more patterns comprises:
slicing an output signal of the gain stage to generate a sliced signal;
analyzing the sliced signal for run length; and
analyzing a plurality of run lengths to generate a vote, and using the vote for comparison to one or more thresholds;
generating a correction to reduce the DC offset based at least partly on the determination.
8. The method of claim 1 , wherein the amplifier further comprises at least one variable gain amplifier, the method further comprising reducing a gain of the at least one variable gain amplifier at least during a time for determining the presence of the one or more patterns.
9. A method for correcting one or more DC offsets in an amplifier, the method comprising:
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier;
generating a correction to reduce the DC offset based at least partly on the determination; and
determining that a DC offset correction process is complete based at least partly on an elapsed time occurring from a previous correction, and passing control to a subsequent gain stage in the amplifier.
10. The method of claim 1 , further comprising determining that a digital-to-analog converter (DAC) resolution limit has been reached, and passing control to a subsequent gain stage in the amplifier.
11. An apparatus comprising:
a gain stage having an output;
a slicer configured to slice the output signal of the gain stage to generate a 1-bit sliced signal, wherein symbols of the 1-bit sliced signal comprises a first state or a second state;
a pattern matching detector configured to analyze the sliced signal for run length, wherein a run length comprises a count of consecutive runs of the first state or the second state, wherein a run length of at least a threshold for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on a count of the run length of the first state or the second state.
12. The apparatus of claim 11 , wherein the correction circuit further comprises a digital to analog converter (DAC), wherein the pattern matching detector is configured to adjust an output voltage of a digital to analog converter (DAC) based at least partly on one or more observed run length patterns.
13. The apparatus of claim 11 , wherein the pattern matching detector is configured to compare the run length to one or more fixed thresholds to determine whether to make a correction.
14. An apparatus comprising:
a gain stage having an output; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on the determination, wherein the correction circuit comprises:
a 1-bit slicer configured to generate a sliced signal from the output signal of the gain stage; and
a pattern matching detector to analyze the sliced signal for run length, wherein the pattern matching detector is configured to compare the run length to one or more thresholds, and is further configured to vary the one or more thresholds to reduce false positive corrections.
15. An apparatus comprising:
a gain stage having an output; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on the determination, wherein the correction circuit comprises:
a 1-bit slicer configured to generate a sliced signal from the output signal of the gain stage; and
a pattern matching detector to analyze the sliced signal for run length, wherein the pattern matching detector is configured to calculate average values of run lengths for comparison to one or more thresholds to determine whether to make a correction.
16. An apparatus comprising:
a gain stage having an output; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on the determination, wherein the correction circuit comprises:
a 1-bit slicer configured to generate a sliced signal from the output signal of the gain stage; and
a pattern matching detector to analyze the sliced signal for run length, wherein the pattern matching detector is configured to integrate values of run lengths and to compare both integrated values and instantaneous run length values to one or more thresholds to determine whether to make correction.
17. An apparatus comprising:
a gain stage having an output; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on the determination, wherein the correction circuit comprises:
a 1-bit slicer configured to generate a sliced signal from the output signal of the gain stage; and
a pattern matching detector to analyze the sliced signal for run length, wherein the pattern matching detector is configured to analyze a plurality of run lengths to generate a vote, and to compare the vote to one or more thresholds to determine whether to make a correction.
18. The apparatus of claim 11 , wherein the gain stage has variable gain, wherein the correction circuit is further configured to reduce a gain of the variable-gain gain stage when the correction circuit is active.
19. An apparatus comprising:
a gain stage having an output; and
a correction circuit configured to determine the presence of one or more patterns associated with DC offsets from an output of the gain stage, and to generate a correction to reduce a DC offset based at least partly on the determination, wherein the correction circuit is further configured to determine that a DC offset correction process is complete based at least partly on an elapsed time occurring from a previous correction, and is configured to pass control to a subsequent gain stage of the apparatus in response to the determination of elapsed time.
20. The apparatus of claim 11 , wherein the correction circuit further comprises a digital-to-analog converter (DAC), wherein the correction circuit is configured to determine that a resolution limit of the DAC has been reached, and is further configured to pass control to a subsequent gain stage of the apparatus.
21. The apparatus of claim 11 , wherein the apparatus further comprises a direct conversion receiver.
22. An apparatus for correcting one or more DC offsets in an amplifier, the apparatus comprising:
means for slicing an output signal of a gain stage of the amplifier to generate a 1-bit sliced signal, wherein symbols of the 1-bit sliced signal comprise a first state or a second state, wherein slicing is performed by electronic hardware;
means for determining the presence of one or more patterns associated with DC offsets from the output of a gain stage of the amplifier, wherein the determining means analyzes the 1-bit sliced signal for run length, wherein a run length comprises a count of consecutive runs of the first state or the second state, wherein a run length of at least a threshold value for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively; and
means for providing an adjustment to correct the DC offset based at least partly on a count of the run length of the first state or the second state.
23. A computer readable medium which stores a computer program that embodies a method of correcting one or more DC offsets in an amplifier, the method comprising:
receiving run length information generated from counting symbols of consecutive runs of a first state or a second state of a 1-bit sliced signal, wherein the output signal of a gain stage of the amplifier is sliced to generate the 1-bit sliced signal, wherein a run length of at least a threshold value for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively;
determining the presence of one or more patterns associated with DC offsets from an output of a gain stage of the amplifier by analyzing run lengths of the 1-bit sliced signal; and
generating a correction to reduce the DC offset based at least partly on a count of the run length of the first state or the second state.