Method and apparatus for improving the signal integrity of high-speed serial data receivers using coupled inductors
View Patent ↗Methods and apparatus improve the signal integrity of high-speed integrated circuits. Disclosed is a passive network for an input to a receiver. One embodiment of the passive network has two coupled inductors to improve both return loss and insertion loss characteristics. A shunt inductor is connected in series with the termination resistance, while a series inductor is placed in series between the pad and receiver circuitry. By exploiting deliberately-introduced mutual coupling between these two inductors, an area-efficient passive network is created that improves both the return loss and input bandwidth.
1. An apparatus comprising:
an integrated circuit assembly;
an input pad disposed on the integrated circuit assembly, wherein the input pad is coupled to a first node;
a primary electrostatic discharge (ESD) protection circuit of the integrated circuit assembly, wherein the primary ESD protection circuit is coupled to the first node;
a shunt inductor having a first end and a second end, wherein the first end of the shunt inductor is directly coupled to the first node;
a termination resistor with an end coupled to a second end of the shunt inductor;
a secondary ESD protection circuit of the integrated circuit assembly, wherein the secondary ESD protection circuit is coupled to a second node;
a receiver having an input coupled to the second node, wherein the receiver is configured to receive a serial data signal;
a current-limiting resistor having a first end coupled to the second node and a second end coupled to a third node; and
a series inductor having a first end and a second end, wherein the first end is coupled to the first node and wherein the second end is coupled to the third node.
2. The apparatus of claim 1 , wherein the shunt inductor and the series inductor substantially overlap physically such that the shunt inductor and the series inductor deliberately exhibit mutual coupling.
3. The apparatus of claim 1 , wherein the shunt inductor and the series inductor substantially overlap physically such that the shunt inductor and the series inductor deliberately exhibit mutual coupling, wherein the voltage polarity of the mutual coupling is aligned such that the first node of the shunt inductor and the first node of the series inductor are in-phase with respect to voltage induced by magnetic coupling.
4. The apparatus of claim 1 , wherein the shunt inductor and the series inductor have a coupling coefficient k of at least 0.2 in magnitude.
5. The apparatus of claim 1 , wherein the shunt inductor and the series inductor have a coupling coefficient k between 0.3 and 0.6 in magnitude.
6. The apparatus of claim 1 , wherein the shunt inductor and the series inductor have a coupling coefficient k between 0.45 and 0.7 in magnitude.
7. The apparatus of claim 1 , wherein the shunt inductor and the series inductor have a coupling coefficient k between 0.5 and 0.85 in magnitude.
8. The apparatus of claim 1 , wherein the shunt inductor and the series inductor have a coupling coefficient k between −0.85 and 0.85.
9. The apparatus of claim 1 , wherein the first node is routed such that the primary ESD protection circuit is disposed in a signal path between the input pad and any of the first end of the shunt inductor or the first end of the series inductor.
10. The apparatus of claim 1 , wherein the shunt inductor has at least 0.1 nanohenries (nH) of inductance, and wherein the series inductor has at least 0.1 nH of inductance.
11. The apparatus of claim 1 , wherein the input pad, the primary ESD protection circuit, the shunt inductor, the termination resistor, the secondary ESD protection circuit, the receiver, and the series inductor, form a circuit for a single-ended input signal, the termination resistor having a resistance being matched to an intended transmission channel, wherein a second end of the termination resistor is coupled to a voltage reference.
12. The apparatus of claim 1 , wherein the input pad, the primary ESD protection circuit, the shunt inductor, the secondary ESD protection circuit, the receiver and the series inductor form a circuit for a positive portion of a differential input signal, wherein the termination resistor has a resistance of about twice the characteristic impedance of an intended transmission channel, further comprising:
a second input pad disposed on the integrated circuit assembly, wherein the second input pad is coupled to a fourth node, wherein the second input pad is configured to receive a negative portion of the differential input signal;
a second primary ESD protection circuit of the integrated circuit assembly, wherein the second primary ESD protection circuit is coupled to the fourth node;
a second shunt inductor having a first end and a second end, wherein the first end is coupled to the fourth node, wherein the second end is coupled to a second end of the termination resistor;
a second secondary ESD protection circuit of the integrated circuit assembly, wherein the second secondary ESD protection circuit is coupled to a fifth node;
a second current-limiting resistor having a first end coupled to the fifth node and a second end coupled to a sixth node;
a second series inductor having a first end and a second end, wherein the first end is coupled to the fourth node and wherein the second end is coupled to the sixth node.
13. The apparatus of claim 12 , wherein the shunt inductor and the series inductor, and the second shunt inductor and the second series inductor have a coupling coefficient k having an absolute value of at least 0.2.
14. The apparatus of claim 12 , wherein the shunt inductor and the series inductor, and the second shunt inductor and the second series inductor have a coupling coefficient k that is negative and has an absolute value of at least 0.2.
15. The apparatus of claim 1 , wherein the current-limiting resistor comprises parasitic trace resistance, explicit resistance, or both parasitic trace resistance and explicit resistance.
16. The apparatus of claim 1 , wherein:
the input pad is directly coupled to the first node;
the first end of the series inductor is directly coupled to the first node; and
the second end of the series inductor is directly coupled to the third node.
17. An apparatus comprising:
an integrated circuit assembly;
an input pad disposed on the integrated circuit assembly, wherein the input pad is coupled to a first node;
a primary electrostatic discharge (ESD) protection circuit of the integrated circuit assembly, wherein the primary ESD protection circuit is coupled to the first node;
a termination resistor with an end coupled to the first node;
a single secondary ESD protection circuit of the integrated circuit assembly, wherein the secondary ESD protection circuit is coupled to a second node;
a receiver having an input coupled to the second node, wherein the receiver is configured to receive a serial data signal;
a current-limiting resistor having a first end coupled to the second node and a second end coupled to a third node; and
a single series inductor having a first end and a second end, wherein the first end is coupled to the first node and wherein the second end is coupled to the third node, wherein there are no other inductors between the first node and the second node than the single series inductor, wherein the first node is routed such that the primary ESD protection circuit is disposed in a signal path between the input pad and the first end of the series inductor.
18. The apparatus of claim 17 , wherein the series inductor has at least 0.1 nanohenries (nH) of inductance.
19. The apparatus of claim 17 , wherein the input pad, the primary ESD protection circuit, the termination resistor, the secondary ESD protection circuit, the receiver, and the series inductor, form a circuit for a single-ended input signal, wherein the termination resistor has a resistance being matched to an intended transmission channel, wherein a second end of the termination resistor is coupled to a voltage reference.
20. The apparatus of claim 17 , wherein the input pad, the primary ESD protection circuit, the secondary ESD protection circuit, the receiver, and the series inductor, form a circuit for a positive portion of a differential input signal, wherein the termination resistor has a resistance of about twice the characteristic impedance of an intended transmission channel, further comprising:
a second input pad disposed on the integrated circuit assembly, wherein the second input pad is coupled to a fourth node, wherein the second input pad is configured to receive a negative portion of the differential input signal;
a second primary ESD protection circuit of the integrated circuit assembly, wherein the second primary ESD protection circuit is coupled to the fourth node;
a second secondary ESD protection circuit of the integrated circuit assembly, wherein the second secondary ESD protection circuit is coupled to a fifth node;
a second current-limiting resistor having a first end coupled to the fifth node and a second end coupled to a sixth node;
a second series inductor having a first end and a second end, wherein the first end is coupled to the fourth node and wherein the second end is coupled to the sixth node.
21. The apparatus of claim 17 , wherein the current-limiting resistor comprises parasitic trace resistance, explicit resistance, or both parasitic trace resistance and explicit resistance.