IP Library Granted Patent US 8,601,169
Granted Patent B1
US 8,601,169 · App. 13/288,619 · Granted Dec 3, 2013

Method and apparatus for a multi-engine descriptor controller for distributing data processing tasks across the engines

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Quick Facts
Patent No.
US 8,601,169
App. No.
13/288,619
Granted
Dec 3, 2013
Kind
B1
Abstract

A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Claims (28)

1. A method of processing commands in a multi-engine storage controller system, comprising:

queuing, in order as received, input segments from multiple input streams, each input segment requiring an associated processing operation, including identifying the input stream to which each input segment belongs;

for each input segment: determining if one of a plurality of processing engines of the multi-engine storage controller system is idle, and that no frame of the input stream to which the input segment belongs is currently scheduled on any other of the plurality of processing engines;

scheduling the input segment, for processing according to its associated processing operation, onto the idle one of a plurality of processing engines;

reading command pointers associated with each of the multiple input streams to determine command descriptors associated with each input segment of each of the multiple input streams; and

reading command descriptors and command contexts associated with each of the multiple input streams from a command memory.

2. The method of claim 1 , wherein scheduling the input segment of one of the multiple input streams is independent of scheduling input segments of another of the multiple input streams.

3. The method of claim 1 , wherein reading pointers associated with each of the multiple input streams is performed concurrently.

4. The method of claim 1 , wherein reading the command pointers comprises reading command pointers from a command post queue.

5. The method of claim 1 , wherein reading the command descriptors and command contexts comprises fetching the command descriptors and command contexts from a command memory in accordance with the command pointers.

6. The method of claim 1 , further comprising: updating the command pointers and command contexts after processing of the input segment by one of the plurality of processing engines to indicate completion of the processing operation.

7. The method of claim 6 , further comprising:

writing updated command pointers and writing command contexts associated with each of the multiple input streams to the command memory;

reordering processed input segments based on relative sequence within the input stream to which they belong; and

writing the ordered processed input segments of the input stream to a command complete queue.

8. A multi-engine storage controller system, comprising:

a plurality of processing engines;

a descriptor read controller including:

a command scheduler configured to schedule input segments from multiple input streams for processing on the plurality of processing engines, each input segment requiring an associated processing operation and including an identification of its respective input stream, the command scheduler determining, for each input segment, if one of the plurality of processing engines is idle, and that no frame of its respective input stream is currently scheduled on any other of the plurality of processing engines, and scheduling the input segment, for processing according to its associated processing operation, onto the idle one of a plurality of processing engines;

wherein the descriptor read controller further includes a command read controller to read command pointers from a command post queue and provide the command pointers associated with each of the plurality of input segments to the command scheduler, and to read command descriptors and command contexts associated with each command pointer from a command memory, and provide the command descriptors and the command contexts to input buffers associated with each of the plurality of processing engines.

9. The system of claim 8 , wherein the command read controller is configured to concurrently read pointers associated with each of the multiple input streams.

10. The system of claim 8 , wherein the command read controller is configured to read the command descriptors and the command contexts by fetching the command descriptors and the command contexts from a command memory in accordance with the command pointers.

11. The system of claim 8 , further comprising a descriptor write controller configured to update the command pointers and the command contexts after processing of the input segment by one of the plurality of processing engines to indicate completion of the processing operation.

12. The system of claim 11 , wherein the descriptor write controller is configured to:

write the updated command pointers and the updated command contexts associated with each of the multiple input streams to the command memory;

reorder processed input segments based on relative sequence within the input stream to which they belong; and

write the ordered processed input segments of the input stream to a command complete queue.

13. A non-transitory computer program product having a computer readable program code tangibly embodied therein which, when executed, causes a processor to perform the method of claim 1 .

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
CHANGE OF NAME Recorded Mar 22, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 038213/0291 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2011
From: PARAGAONKAR, CHETAN; TAN, KUAN HUA
To: PMC-SIERRA US, INC.
Reel/Frame 027281/0701 →