IP Library Granted Patent US 7,107,381
Granted Patent B2
US 7,107,381 · App. 10/301,369 · Granted Sep 12, 2006

Flexible data transfer to and from external device of system-on-chip

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Quick Facts
Patent No.
US 7,107,381
App. No.
10/301,369
Granted
Sep 12, 2006
Kind
B2
Abstract

In a bus interface unit, a first communications interface is provided for the coupling of a first plurality of peripheral devices of different device types to facilitate communication with a selected one of the first plurality of peripheral devices of different device types. In addition, a second communications interface is provided for coupling to a first bus of an integrated circuit (IC) to facilitate communication with a selected one of a second plurality of devices of the IC, via the first bus. A controller is provided for the coupling of the first and second communications interfaces to facilitate communications between selected ones of the first and second plurality of devices, dynamically selecting and employing a communication protocol consistent with the device type of the selected one of the first plurality of peripheral devices. The bus interface unit has particular application to interfacing external devices with the core of an SOC.

Claims (32)

1. An integrated circuit comprising:

a plurality of functional blocks;

a bus coupled to the plurality of functional blocks;

a data transfer unit coupled to the bus;

a first input/output interface block coupled to the data transfer unit and a plurality of devices, the first input/output interface block to facilitate transfer of data from the plurality of devices to selected ones of the plurality of functional blocks, the transfer occurring at a first data size granularity; and

a second input/output interface block coupled to the data transfer unit and the plurality of devices to facilitate transfer of data from the plurality of devices to selected ones of the plurality of functional blocks, the transfer occurring at a second data size granularity.

2. The integrated circuit of claim 1 wherein the second input/output interface block further to facilitate the transfer of data from a first selected one of the plurality of functional blocks to a second selected one of the plurality of functional blocks.

3. The integrated circuit of claim 1 wherein the second input/output interface block to facilitate transfers to a selected one of the plurality of functional blocks such that locations of the selected one of the plurality of functional blocks fill with a predetermined pattern.

4. The integrated circuit of claim 1 wherein the second input/output interface block comprises a byte aligner to align transferred data based at least on a source and a destination address.

5. The integrated circuit of claim 1 wherein the second input/output interface block is coupled to the plurality of devices through the first input/output interface block.

6. The integrated circuit of claim 1 wherein the second input/output interface block comprises two memory units.

7. The integrated circuit of claim 6 wherein a first memory unit is coupled to the plurality of devices and the second memory unit is coupled to the selected ones of the plurality of functional blocks.

8. The integrated circuit of claim 1 wherein second data size granularity is larger that the first data size granularity.

9. The integrated circuit of claim 1 wherein the second input/output interface block is configurable to perform any byte to any byte transfers between the plurality of devices and a selected one of the plurality of functional blocks.

10. The integrated circuit of claim 1 wherein the second input/output interface block to facilitate a protocol conversion for the transferred data.

11. In an integrated circuit comprising a plurality of functional blocks and a plurality of input/output interface blocks coupled to a plurality of devices, a method comprising:

transferring data from a selected one of the plurality of devices to a first of the input/output interface blocks at a first data size granularity;

transferring the data from the first of the input/output interface blocks to a second of the input/output interface blocks; and

transferring the data from the second of the input/output interface blocks to a first selected one of the plurality of functional blocks at a second data size granularity.

12. The method of claim 11 wherein the method further comprises a second selected one of the plurality of functional blocks transferring data to the second input/output interface block, and the second input/output interface block further transfers the data a third selected one of the plurality of functional blocks.

13. The method of claim 12 , wherein either the first and the second selected one of the plurality of function blocks is one of the same function block, or the first and the third selected one of the plurality of function blocks is one of the same function block.

14. The method of claim 11 wherein the second input/output interface block facilitates transfers to a selected one of the plurality of functional blocks such that locations of the selected one of the plurality of functional blocks fill with a predetermined pattern.

15. The method of claim 11 wherein the second input/output interface block transfers data in an aligned manner based at least on a source and a destination address.

16. The method of claim 11 wherein the second data size granularity is larger that the first data size granularity.

17. The method of claim 11 wherein the data were initially stored in the selected one of the plurality of devices, starting at a first byte position, and store in the selected one of the plurality of functional blocks, starting at a second byte position.

18. The method of claim 11 wherein a selected one of the first and the second input/output interface block further facilitates a protocol conversion for the transferred data.

19. In an integrated circuit comprising a plurality of functional blocks and a plurality of input/output interface blocks coupled to a plurality of devices, a method comprising:

transferring data from a selected one of the plurality of functional blocks to a first of the input/output interface blocks at a first data size granularity;

transferring the data from the first of the input/output interface blocks to a second of the input/output interface blocks; and

transferring the data from the second of the input/output interface blocks to a first selected one of the plurality of devices at a second data size granularity.

20. The method of claim 19 , wherein the method further comprises a second selected one of the plurality of functional blocks transferring data to the first input/output interface block, and the second input/output interface block further transfers the data to a third selected one of the plurality of functional blocks.

21. The method of claim 20 , wherein either the first and the second selected one of the plurality of function blocks is one of the same function block, or the first and the third selected one of the plurality of function blocks is one of the same function block.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
TERMINATION OF SECURITY AGREEMENT Recorded Feb 14, 2005
From: TRANSAMERICA TECHNOLOGY FINANCE CORPORATION
To: BRECIS COMMUNICATIONS CORP.
Reel/Frame 016824/0393 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2004
From: BRECIS COMMUNICATIONS CORPORATION
To: PMC-SIERRA, INC.
Reel/Frame 015259/0503 →
RELEASE OF SECURITY AGREEMENT Recorded Oct 19, 2004
From: TRANSAMERICA TECHNOLOGY FINANCE CORPORATION
To: BRECIS COMMUNICATIONS CORPORATION
Reel/Frame 015271/0223 →
SECURITY AGREEMENT Recorded Jun 19, 2003
From: BRECIS COMMUNICATIONS CORPORATION
To: TRANSAMERICA TECHNOLOGY FINANCE CORPORATION
Reel/Frame 014172/0322 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2002
From: EARL, JEFFREY S.; APOSTOL JR., GEORGE; CROSS, DOUGLAS A.
To: BRECIS COMMUNICATIONS CORPORATION
Reel/Frame 013519/0169 →