IP Library Granted Patent US 7,656,945
Granted Patent B1
US 7,656,945 · App. 11/538,346 · Granted Feb 2, 2010

Stabilized digital timing recovery using low-complexity equalizer

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Quick Facts
Patent No.
US 7,656,945
App. No.
11/538,346
Granted
Feb 2, 2010
Kind
B1
Abstract

A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique for automatically adjusting the parameters of a digital linear equalizer to compensate for low-pass impairments while maintaining a relatively constant timing characteristic is described.

Claims (50)

1. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein the digital filter comprises a finite impulse response (FIR) filter having three or more FIR filter coefficients, wherein odd coefficients of the FIR filter are nonzero and adaptively adjusted, and wherein even coefficients of the FIR filter are zero or nearly zero regardless of the adjustments to the odd coefficients; and

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter.

2. The apparatus as defined in claim 1 , wherein an input of the adaptive equalizer is operatively coupled to an output of the analog-to-digital converter, and wherein an input of the timing recovery circuit is operatively coupled to an output of the adaptive equalizer, the apparatus further comprising: a decision device coupled to the output of the adaptive equalizer such that the decision device determines a symbol based on the output of the adaptive equalizer.

3. The apparatus as defined in claim 1 , wherein an input of the adaptive equalizer is operatively coupled to an output of the analog-to-digital converter, and wherein an input of the timing recovery circuit is operatively coupled to an output of the adaptive equalizer, the apparatus further comprising a main receiver processing entity coupled to the output of the analog-to-digital converter, and wherein the receiver processing entity is configured to generate symbols.

4. The apparatus as defined in claim 3 , further comprising a pre-processing circuit disposed in the processing path between the analog-to-digital converter and the adaptive equalizer, wherein the pre-processing circuit is configured to modify the output of the analog-to-digital converter adaptively at least partially in response to a control from the main receiver processing entity, wherein the pre-processing circuit is configured to correct at least one of residual DC offset or baseline wander.

5. The apparatus as defined in claim 4 , wherein the pre-processing circuit is integrated with the main receiver processing entity.

6. The apparatus as defined in claim 1 , wherein the timing recovery circuit is further configured to adjust sampling timing based at least partially on the output of the analog-to-digital converter in addition to the output of the adaptive equalizer.

7. The apparatus as defined in claim 1 , wherein the adaptive equalizer comprises a tapped delay line and an adaptation controller, and wherein the timing recovery circuit comprises a timing error detector and an infinite impulse response (IIR) filter.

8. The apparatus as defined in claim 1 , wherein the transmission channel comprises a cable.

9. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein the digital filter is a finite impulse response (FIR) filter having FIR filter coefficients represented by vector h, wherein: h−α·[1 σ β] T , wherein the α and β coefficients are adaptively adjusted coefficients, and the σ coefficient comprises zero or near-zero values; and

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter.

10. The apparatus as defined in claim 9 , wherein the σ coefficient comprises zero.

11. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein the digital filter is a finite impulse response (FIR) filter having FIR filter coefficients represented by vector h, wherein: h=α·[1 σ 1 β 1 σ 2 β 2 σ 3 . . . σ m β m ] T , wherein the α and β x coefficients are adaptively adjusted coefficients and the σ x coefficients comprise zero or near-zero values; and

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter.

12. The apparatus as defined in claim 11 , wherein the σ x coefficients comprise zero.

13. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein an input of the adaptive equalizer is operatively coupled to an output of the analog-to-digital converter;

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter, wherein an input of the timing recovery circuit is operatively coupled to an output of the adaptive equalizer;

a main receiver processing entity coupled to the output of the analog-to-digital converter, and wherein the receiver processing entity is configured to generate symbols;

a pre-processing circuit disposed in the processing path between the analog-to-digital converter and the adaptive equalizer, wherein the pre-processing circuit is configured to modify the output of the analog-to-digital converter adaptively at least partially in response to a first control from the main receiver processing entity; and

a post-processing circuit disposed in the processing path between the adaptive equalizer and the timing recovery circuit, wherein the post-processing circuit is configured to modify the output of the adaptive equalizer adaptively at least partially in response to a second control from the main receiver processing entity.

14. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein an input of the adaptive equalizer is operatively coupled to an output of the analog-to-digital converter;

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter, wherein an input of the timing recovery circuit is operatively coupled to an output of the adaptive equalizer; and

a main receiver processing entity coupled to the output of the analog-to-digital converter, and wherein the receiver processing entity is configured to generate symbols;

wherein the pre-processing circuit and the post-processing circuit are integrated with the main receiver processing entity.

15. An apparatus for adaptively compensating for impairments in a transmission channel, the apparatus comprising:

an analog-to-digital converter, wherein the analog-to-digital converter is configured to sample an input signal from the transmission channel and to provide a digital output of the input signal;

an adaptive equalizer implemented in the digital domain by a digital filter, wherein the equalizer has a band-pass filter characteristic, wherein the adaptive equalizer is configured to receive a digital signal as an input, wherein the digital signal is at least based on the digital output of the analog-to-digital converter, wherein an input of the adaptive equalizer is operatively coupled to an output of the analog-to-digital converter;

a timing recovery circuit operatively coupled at least to an output of the adaptive equalizer, wherein the timing recovery circuit is configured to adjust sampling timing of the analog-to-digital converter, wherein an input of the timing recovery circuit is operatively coupled to an output of the adaptive equalizer;

a main receiver processing entity coupled to the output of the analog-to-digital converter, and wherein the receiver processing entity is configured to generate symbols; and

a post-processing circuit disposed in the processing path between the adaptive equalizer and the timing recovery circuit, wherein the post-processing circuit is configured to modify the output of the adaptive equalizer adaptively at least partially in response to a control from the main receiver processing entity.

16. The apparatus as defined in claim 15 , wherein the post-processing circuit is integrated with the main receiver processing entity.

17. A method of constraining tap coefficients in an adaptive Finite Impulse Response (FIR) filter, the method comprising:

effectively adaptively adjusting at least two filter tap coefficients for the FIR filter; and

maintaining one or more filter tap coefficients in between the at least two adaptively adjusted filter tap coefficients to be zero or nearly zero regardless of the adjustments to the adaptively adjusted filter tap coefficients;

wherein the FIR filter equalizes an output of an analog-to-digital converter to compensate for impairments in a transmission channel.

18. The method as defined in claim 17 , wherein the FIR filter has FIR filter coefficients represented by vector h, wherein: h=α·[1 σ β] T , wherein the α and β coefficients are adaptively adjusted for the effective adaptive adjustment of the at least two filter tap coefficients, and the σ coefficient comprises the one or more filter tap coefficients in between the at least two effectively adaptively adjusted filter tap coefficients.

19. The method as defined in claim 18 , wherein the σ coefficient has a value of zero.

20. The method as defined in claim 17 , wherein the FIR filter has FIR filter coefficients represented by vector h, wherein: h=α·[1 σ 1 β 1 σ 2 β 2 σ 3 . . . σ m β m ] T , wherein the α and β x coefficients are adaptively adjusted for the effective adaptive adjustment of the at least two filter tap coefficients, and the σ x coefficients comprises the one or more filter tap coefficients in between of the adaptively adjusted filter tap coefficients.

21. The method as defined in claim 20 , wherein the σ x coefficients have a value of zero.

22. The method as defined in claim 17 , further comprising adaptively adjusting the coefficients according to at least one of a least mean square (LMS) technique, a recursive least squares (RLS) filtering technique, or a Kalman filtering technique.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
CHANGE OF NAME Recorded Apr 7, 2016
From: PMC-SIERRA, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 038381/0753 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
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SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →