Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers
View Patent ↗Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transmitting data. This permits data tracking circuitry of a receiver to be efficiently tested with a relatively simple loop back test.
1. A built-in self test (BIST) circuit for a data transceiver, the BIST circuit comprising:
a clock synthesis unit (CSU) having a first clock signal as an output;
a parallel-in, serial-out (PISO) circuit configured to receive parallel data and to generate serial data, where a data rate of the serial data corresponds to a serial clock frequency provided to the PISO circuit via a clock signal input;
a multiplexer having at least a first input, a second input, and an output, where the first input is coupled to the first clock signal from the clock synthesis unit (CSU), where the second input is coupled to a second clock signal from an asynchronous clock source, where the output of the multiplexer is coupled to the clock signal input of the PISO circuit, where the multiplexer provides the first input to the clock signal input of the PISO circuit when the data transceiver is in a normal mode and provides the second input to the clock signal input of the PISO circuit when the data transceiver is in a test mode.
2. The BIST circuit as defined in claim 1 , wherein the asynchronous clock source comprises a phase interpolator coupled to the first clock signal, where a control signal to the phase interpolator changes a phase offset between the second clock signal and the first clock signal.
3. The BIST circuit as defined in claim 2 , wherein the phase interpolator further comprises:
a first mixer with inputs coupled to a first phase of the first clock signal and to a first weight;
a second mixer with inputs coupled to a second phase of the first clock signal and to a second weight;
a first summing circuit with inputs coupled to outputs of the first mixer and the second mixer;
a first duty cycle correction circuit with an input coupled to an output of the first summing circuit;
a third mixer with inputs coupled to the first phase of the first clock signal and to the second weight;
a fourth mixer with inputs coupled to the second phase of the first clock signal and to a complement of the first weight;
a second summing circuit with inputs coupled to outputs of the third mixer and the fourth mixer; and
a second duty cycle correction circuit with an input coupled to an output of the second summing circuit.
4. The BIST circuit as defined in claim 3 , wherein the first duty cycle correction circuit and the second duty cycle correction circuit comprise high-pass filter circuits that remove direct current (DC) offsets.
5. The BIST circuit as defined in claim 3 , further comprising digital-to-analog converters having the first weight and the second weight as outputs.
6. The BIST circuit as defined in claim 5 , wherein the digital-to-analog converters correspond to thermometer-code digital-to-analog converters.
7. The BIST circuit as defined in claim 5 , further comprising a state machine operatively coupled to inputs of the digital-to-analog converters for control, wherein the state machine is configured to control the first weight and the second weight of the digital-to-analog converters in a predetermined pattern.
8. The BIST circuit as defined in claim 5 , further comprising an external interface operatively coupled to control inputs of the digital-to-analog converters such that the first weight and the second weight of the digital-to-analog converters are selectable under external control.
9. The BIST circuit as defined in claim 3 , wherein the BIST circuit is embodied in a serializer/deserializer (SerDes) device.
10. The BIST circuit as defined in claim 1 , wherein the asynchronous clock source further comprises a reduced-frequency phase interpolator and a frequency multiplier, where an input of the reduced-frequency phase interpolator is coupled to the first clock signal, which is of a lower frequency than the serial clock frequency provided to the PISO circuit, where an input of the frequency multiplier is coupled to an output of the reduced-frequency phase interpolator, and where an output of the frequency multiplier provides the second clock signal.
11. The BIST circuit as defined in claim 10 , wherein the frequency multiplier corresponds to an exclusive-OR (XOR) gate.
12. The BIST circuit as defined in claim 1 , wherein the asynchronous clock source comprises an analog mixer coupled to the first clock signal and to a modulation signal, where the analog mixer is configured to multiply the first clock signal and the modulation signal to generate the second clock signal.
13. The BIST circuit as defined in claim 1 , wherein the asynchronous clock source comprises a second clock synthesis unit that is configured to generate the second clock signal from a test-mode reference clock signal.
14. The BIST circuit as defined in claim 1 , further comprising a clock recovery unit coupled to a data stream received in a receiver of the data transceiver and coupled to a clock signal from the clock synthesis unit (CSU), wherein the clock recovery unit is configured to track the data stream and generate a sampling clock signal.
15. The BIST circuit as defined in claim 1 , wherein the BIST circuit is embodied in a serializer/deserializer (SerDes) device.
16. A method in a data transceiver of testing tracking of a receiver, the method comprising:
in a normal mode, referencing timing of data bits of an output of a transmitter of the data transceiver to a first clock signal;
in a test mode, referencing timing of the data bits of the output of the transmitter to a second clock signal, where the second clock signal is asynchronous to the first clock signal;
looping back the output of the transmitter to the receiver;
using a third clock signal that is synchronous to the first clock signal and asynchronous to the second clock signal as a timing reference for the receiver;
monitoring an output of the receiver for bit errors;
providing the first clock signal and the second clock signal as inputs to a multiplexer;
coupling an output of the multiplexer to the transmitter of the data transceiver,
where the output of the multiplexer is used by the transmitter as the timing reference;
selecting the first clock signal as the output of the multiplexer in the normal mode; and
selecting the second clock signal as the output of the multiplexer in the test mode.
17. The method as defined in claim 16 , wherein the third clock signal is derived from the first clock signal.
18. The method as defined in claim 16 , wherein the third clock signal is divided by two from the first clock signal.
19. The method as defined in claim 16 , wherein the third clock signal and the first clock signal are the same.
20. The method as defined in claim 16 , further comprising generating the second clock signal from the first clock signal with a phase interpolator.
21. The method as defined in claim 20 , further comprising:
frequency dividing the first clock signal;
providing the frequency divided first clock signal as an input to the phase interpolator;
operating the phase interpolator at a substantially lower frequency than either the first clock signal or the second clock signal; and
frequency multiplying an output of the phase interpolator to generate the second clock signal.
22. The method as defined in claim 21 , further comprising using an exclusive-OR (XOR) gate to frequency multiply the output of the phase interpolator.
23. The method as defined in claim 16 , further comprising generating the second clock signal from the first clock signal with an analog mixer.
24. The method as defined in claim 16 , wherein the second clock signal is frequency offset from the first clock signal.
25. The method as defined in claim 16 , wherein the second clock signal is repeatedly phase offset from the first clock signal to generate a jitter pattern between the second clock signal and the first clock signal.
26. The method as defined in claim 16 , further comprising generating the first clock signal and the second clock signal from separate clock synthesizer units (CSUs).
27. The method as defined in claim 16 , wherein the data transceiver is embodied in a serializer/deserializer (SerDes) device.