IP Library Granted Patent US 8,413,006
Granted Patent B1
US 8,413,006 · App. 12/705,304 · Granted Apr 2, 2013

Error detection and correction in data and control words

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Quick Facts
Patent No.
US 8,413,006
App. No.
12/705,304
Granted
Apr 2, 2013
Kind
B1
Abstract

A method and system are provided to detect and correct errors in the Interlaken block code overhead bits. Specifically, a method is provided for determining the original transmitted information with a very high probability of correct interpretation. These approaches can also characterized by their minimal complexity. Further, such a method can operate on the received information in a manner that does not require consideration of special cases. Also, the method does not require the source to send any extra information or alter its current behavior in any way. Thus, the approaches described herein are compatible with all existing Interlaken sources and can provide immediate benefits.

Claims (46)

1. A method of correcting bit errors in a word having overhead bits and payload bits, the word being communicated in accordance with a communication protocol, the method comprising:

detecting a received overhead bit pattern in the overhead bits;

providing an overhead bit correction table, including a plurality of candidate corrective overhead bit patterns, the plurality of candidate corrective overhead bit patterns being based on syntactically valid overhead bit patterns associated with the received overhead bit pattern;

selecting, from the overhead bit correction table, a valid candidate corrective overhead bit pattern having a lowest probability of error as a replacement overhead bit pattern; and

replacing the received overhead bit pattern with the replacement overhead bit pattern.

2. The method of claim 1 further comprising generating the overhead bit correction table.

3. The method of claim 2 wherein generating the overhead bit correction table comprises:

generating potential candidates for correcting the received overhead bit pattern, the potential candidates including single bit error and error free potential candidates with respect to the received overhead bit pattern; and

generating the plurality of candidate corrective overhead bit patterns by eliminating syntactically illegal potential candidates from the generated potential candidates.

4. The method of claim 3 wherein generating the potential candidates and generating the plurality of candidate corrective overhead bit patterns are performed for each possible received overhead bit pattern in the communication protocol.

5. The method of claim 1 wherein selecting the valid corrective overhead bit pattern having the lowest probability of error comprises eliminating from consideration semantically invalid candidate corrective overhead bit patterns.

6. The method of claim 5 wherein the invalid corrective overhead bit patterns are eliminated from consideration in response to a determination that the received payload bits are unexpected payload bits with respect to the received overhead bit pattern.

7. The method of claim 6 further comprising comparing the received payload bits to expected valid payload bits associated with the received overhead bit pattern, and determining whether the received payload bits are unexpected payload bits with respect to the received overhead bit pattern.

8. The method of claim 5 wherein the received word has associated timing information, and wherein the semantically invalid candidate corrective overhead bit patterns are eliminated from consideration with respect to unexpected overhead bit patterns for the associated timing information.

9. The method of claim 5 wherein the semantically invalid candidate corrective overhead bit patterns are eliminated from consideration with respect to a temporal neighboring word context.

10. The method of claim 5 wherein the semantically invalid candidate corrective overhead bit patterns are eliminated from consideration with respect to a spatial neighboring word context.

11. The method of claim 1 wherein the overhead bits comprise bits 63 , 64 , 65 and 66 of an Interlaken interface block.

12. An overhead bit correction apparatus to correct bit errors in a packet having overhead bits and payload bits, comprising:

an overhead bit pattern detector arranged to detect a received overhead bit pattern in the overhead bits;

an overhead bit correction table including a plurality of candidate corrective overhead bit patterns, the candidate corrective overhead bit patterns being based on syntactically valid overhead bit patterns associated with the received overhead bit pattern;

a selector arranged to select, from the overhead bit correction table, a valid candidate corrective overhead bit pattern having a lowest probability of error as a replacement overhead bit pattern; and

wherein the apparatus is arranged to replace the received overhead bit pattern with the replacement overhead bit pattern.

13. The apparatus of claim 12 further comprising a candidate generator arranged to generate the plurality of candidate corrective overhead bit patterns in the overhead bit correction table.

14. The apparatus of claim 13 wherein the candidate generator is arranged to:

generate potential candidates for correcting the received overhead bit pattern, the potential candidates including single bit error and error free potential candidates with respect to the received overhead bit pattern; and

generate the plurality of candidate corrective overhead bit patterns by eliminating syntactically illegal potential candidates from the generated potential candidates.

15. The apparatus of claim 13 wherein the candidate generator is arranged to generate the potential candidates and to generate the plurality of candidate corrective overhead bit patterns for each possible received overhead bit pattern in the communication protocol.

16. The apparatus of claim 13 wherein the candidate generator is in communication with a database in order to determine which candidate corrective overhead bit patterns are syntactically valid.

17. The apparatus of claim 12 wherein the selector is arranged to eliminate from consideration semantically invalid candidate corrective overhead bit patterns, as part of selecting the valid corrective overhead bit pattern having the lowest probability of error.

18. The apparatus of claim 17 wherein the selector eliminates from consideration the invalid corrective overhead bit patterns in response to a determination that the received payload bits are unexpected payload bits with respect to the received overhead bit pattern.

19. The apparatus of claim 18 wherein the selector compares the received payload bits to expected valid payload bits associated with the received overhead bit pattern, and determines whether the received payload bits are unexpected payload bits with respect to the received overhead bit pattern.

20. The apparatus of claim 17 wherein the received word has associated timing information, and wherein the selector eliminates the semantically invalid candidate corrective overhead bit patterns from consideration with respect to unexpected overhead bit patterns for the associated timing information.

21. The apparatus of claim 17 wherein the selector eliminates the semantically invalid candidate corrective overhead bit patterns from consideration with respect to a temporal neighboring word context.

22. The apparatus of claim 17 wherein the selector eliminates the semantically invalid candidate corrective overhead bit patterns from consideration with respect to a spatial neighboring word context.

23. The apparatus of claim 12 wherein the overhead bits comprise bits 63 , 64 , 65 and 66 of an Interlaken interface block.

24. The apparatus of claim 12 wherein the selector is in communication with a database to assist the selector in selecting the candidate having the least probability of error in the interpretation of payload data.

25. The apparatus of claim 12 wherein the selector is in communication with a payload error protection system, and adapted to negotiate therewith in order to select or determine the candidate with the lowest probability of error.

26. A method of detecting a single bit error in a packet having overhead bits and payload bits, comprising:

detecting a received overhead bit pattern in the overhead bits;

performing an overhead bit pattern analysis based on the detected overhead bit pattern;

determining, based on a result of the overhead bit pattern analysis, whether a correctable error has occurred in the overhead bits;

determining that the received payload bits are unexpected payload bits with respect to the received overhead bit pattern.

27. The method of claim 26 further comprising comparing the received payload bits to expected valid payload bits associated with the received overhead bit pattern.

28. The method of claim 26 wherein performing the overhead bit pattern analysis comprises considering associated timing information with respect to the received overhead bit pattern.

29. The method of claim 26 wherein performing the overhead bit pattern analysis comprises considering a temporal neighboring word context with respect to the received overhead bit pattern.

30. The method of claim 26 wherein performing the overhead bit pattern analysis comprises considering a spatial neighboring word context with respect to the received overhead bit pattern.

Assignments (20)
CHANGE OF NAME Recorded Sep 22, 2025
From: OPEN SILICON INC.
To: ALPHAWAVE SEMI, INC.
Reel/Frame 072326/0405 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
CHANGE OF NAME Recorded Mar 22, 2016
From: PMC-SIERRA, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 038067/0428 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2010
From: WEBER, MATTHEW DAVID
To: OPEN-SILICON, INC.
Reel/Frame 023940/0434 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2010
From: MOK, WINSTON KI-CHEONG; GORSHE, STEVEN SCOTT
To: PMC-SIERRA, INC.
Reel/Frame 023940/0477 →