Decoupling and pipelining of multiplexer loop in parallel processing decision-feedback circuits
View Patent ↗This invention discloses circuit and methods to decouple and pipeline block decision feedback multiplexer (MUX) loop in parallel processing decision feedback circuits. In one embodiment of this invention, a block decision feedback MUX loop consists of a pipelined intra-block decision feedback MUX stage and an inter-block decision feedback MUX stage to handle intra-block decision feedback selection and inter-block decision feedback selection separately. In the pipelined intra-block decision feedback stage, inter-block dependency is eliminated to enable pipelining. In another embodiment of this invention for moderately timing-critical parallel processing decision feedback circuits, a block decision feedback MUX loop is piecewise split into multiple series connected segments that each segment contains parallel branches. The intra-segment decision feedback selections of different segments are decoupled and processed in parallel. The selections of final decision signals of different branches in a segment are parallelized.
1. A computer-implemented method of parallel processing digital input signal vectors of an input block of a synchronous decision feedback circuit, the input block having N branches, the computer-implemented comprising:
pre-computing N input signal vectors each having M entries, each entry being a possible value of one of the N branches;
evaluating all possible values of the input signal vectors according to a set of M pre-assigned decision feedback signals to provide M intra-block decision signal vectors, each intra-block decision signal vector having N entries; and
processing each of the entries of each of the intra-block decision signal vectors according to an inter-block decision feedback signal to select N outputs for the input block, the inter-block decision feedback signal being based on outputs for a previous block.
2. The computer-implemented method of claim 1 , further comprising outputting the selected N outputs for the input block as an output block.
3. The computer-implemented method of claim 2 , wherein evaluating all possible values of the input signal vectors comprises:
evaluating possible values of one of the input signal vectors according to one of the pre-assigned decision feedback signals to select a first value of one of the intra-block decision signal vectors;
updating the one of the pre-assigned decision feedback signals to incorporate the first value; and
evaluating possible values of a next one of the input signal vectors according to the updated pre-assigned decision feedback signal to select a next value of the one of the intra-block decision signal vectors.
4. The computer-implemented method of claim 3 , further comprising repeating the steps of updating the pre-assigned decision feedback signal and evaluating possible values of a next one of the input signal vectors for each of the input signal vectors.
5. The computer-implemented method of claim 4 , further comprising synchronizing the outputs of the selected values of the one of the intra-block decision signal vectors.
6. The computer-implemented method of claim 5 , further comprising generating a next inter-block decision feedback signal based on the outputs for the input block.
7. A synchronous circuit for parallel processing digital input signal vectors of an input block having N branches, comprising:
a pre-computation stage for pre-computing N input signal vectors each having M entries, each entry being a possible value of one of the N branches;
a pipelined intra-block decision feedback stage for evaluating all possible values of the input signal vectors according to a set of M pre-assigned decision feedback signals to provide M intra-block decision signal vectors, each intra-block decision signal vector having N entries; and
an inter-block decision feedback stage for processing each of the entries of each of the intra-block decision signal vectors according to an inter-block decision feedback signal to select N outputs for the input block, the inter-block decision feedback signal being based on outputs for a previous block.
8. The synchronous circuit of claim 7 , wherein the pipelined intra-block decision feedback stage comprises M parallel MUX chains.
9. The synchronous circuit of claim 8 , wherein the M parallel MUX chains are for evaluating possible values of one of the input signal vectors according to one of the pre-assigned decision feedback signals to select a first value of one of the intra-block decision signal vectors, updating the one of the pre-assigned decision feedback signals to incorporate the first value, and evaluating possible values of a next one of the input signal vectors according to the updated pre-assigned decision feedback signal to select a next value of the one of the intra-block decision signal vectors.
10. The synchronous circuit of claim 9 , wherein the inter-block decision feedback stage comprises N parallel MUX's.
11. The synchronous circuit of claim 10 , wherein the circuit is any one of a decision feedback equalizer, a decision feedback decoder or a differential pulse code modulation circuit.
12. A computer-implemented method of parallel processing digital input signal vectors of an input block of a synchronous decision feedback circuit, the input block having N branches, the computer-implemented comprising:
pre-computing N input signal vectors each having M entries, each entry being a possible value of one of the N branches;
evaluating all possible values of a first subset of the input signal vectors according to an inter-block decision feedback signal vector to select outputs for the first subset of the input signal vectors, the inter-block decision feedback signal vector being based on outputs of a previous block;
evaluating all possible values of a second subset of the input signal vectors according to a set of M pre-assigned decision feedback signals to provide a set of M intra-block decision signal vectors each having M entries;
processing each of the entries of the set of M intra-block decision signal vectors according to the outputs of the first subset to select an output for each of the set of M intra-block decision signal vectors.
13. The computer-implemented method of claim 12 , further comprising outputting the selected outputs for each of the N input signal vectors as an output block.
14. The computer-implemented method of claim 13 , wherein evaluating all possible values of the second subset of the input signal vectors comprises:
evaluating possible values of one of the subset of input signal vectors according to one of the set of pre-assigned decision feedback signals to select a first value of one of the set of intra-block decision vectors;
updating the one of the set of pre-assigned decision feedback signals to incorporate the first value; and
evaluating possible values of a next one of the input signal vectors according to the updated pre-assigned decision feedback signal to select a next value of the one of the intra-block decision signal vectors.
15. The computer-implemented method of claim 14 , further comprising synchronizing the outputs of the selected values of the one of the intra-block decision signal vectors.
16. The computer-implemented method of claim 15 , further comprising repeating the steps of updating the pre-assigned decision feedback signal and evaluating possible values of a next one of the input signal vectors for each of the N input signal vectors.
17. The computer-implemented method of claim 16 , further comprising:
evaluating all possible values of a third subset of the input signal vectors according to a next set of M pre-assigned decision feedback signals to provide a next set of M intra-block decision signal vectors each having M entries, and
processing each of the entries of the next set of M intra-block decision signal vectors according to the outputs of the second subset to select an output for each of the next set of M intra-block decision signal vectors.
18. The computer-implemented method of claim 17 , further comprising generating a next inter-block decision feedback signal based on the outputs for the input block.
19. A synchronous circuit for parallel processing digital input signal vectors of an input block having N branches, comprising:
a pre-computation stage for pre-computing N input signal vectors each having M entries, each entry being a possible value of one of the N branches;
a first segment for evaluating all possible values of a first subset of the input signal vectors according to an inter-block decision feedback signal vector to select output values for the first subset of the input block, the inter-block decision feedback signal vector being based on outputs of a previous block; and
a second segment having
a decoupled intra-segment decision feedback stage for evaluating all possible values of a second subset of the input signal vectors according to a set of M pre-assigned decision feedback signals to provide a set of M intra-block decision signal vectors each having M entries, and
a parallel inter-segment decision feedback stage for processing each of the entries of the set of M intra-block decision signal vectors according to the outputs of the first subset to select an output for each of the set of M intra-block decision signal vectors.
20. The synchronous circuit of claim 19 , further comprising a third segment having
a decoupled intra-segment decision feedback stage for evaluating all possible values of a third subset of the input signal vectors according to a next set of M pre-assigned decision feedback signals to provide a next set of M intra-block decision signal vectors each having M entries, and
a parallel inter-segment decision feedback stage for processing each of the entries of the next set of M intra-block decision signal vectors according to the outputs of the second subset to select an output for each of the next set of M intra-block decision signal vectors.
21. The synchronous circuit of claim 20 , wherein the first segment is a MUX chain.
22. The synchronous circuit of claim 21 , wherein the decoupled intra-segment decision feedback stages comprise M parallel MUX chains.
23. The synchronous circuit of claim 22 , wherein the parallel inter-segment decision feedback stages comprise parallel MUX's, each corresponding to a pre-assigned decision feedback signal.
24. The synchronous circuit of claim 23 , wherein the circuit is any one of a decision feedback equalizer, a decision feedback decoder or a differential pulse code modulation circuit.