High speed I/O pad and pad/cell interconnection for flip chips
View Patent ↗Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.
1. A semiconductor die for use in flip chip applications comprising an array of I/O pads, said array comprising at least one signal pad and a plurality of non-signal pads, said plurality of non-signal pads being made up of ground pads and power pads, wherein said signal pad is surrounded by said non-signal pads and wherein said signal pad is connected to an I/O cell by a signal trace.
2. The semiconductor die of claim 1 , wherein said array of I/O pads is arranged to form a right angled grid.
3. The semiconductor die of claim 1 , wherein said signal pad comprises two differential signal pads and wherein each of said differential signal pads is connected to said I/O cell by a signal trace.
4. The semiconductor die of claim 1 , wherein said signal pad is surrounded by eight of said non-signal pads.
5. The semiconductor die of claim 1 , wherein the non-signal pads nearest said signal pad are ground pads.
6. The semiconductor die of claim 1 , wherein said non-signal pads are ground pads.
7. The semiconductor die of claim 4 , wherein 4 of said non-signal pads nearest said signal pad are ground pads.
8. The semiconductor die of claim 5 , wherein said ground pads are connected to one another by a metal trace to form a ground pad ring.
9. The semiconductor die of claim 4 , wherein said signal pad is surrounded by 8 ground pads and said 8 ground pads are connected to one another by a metal trace to form a ground pad ring.
10. The semiconductor die of claim 1 , wherein said non-signal pads are power pads.
11. The semiconductor die of claim 8 , wherein said ground pad ring is connected to a conductor-backed ground coplanar waveguide, said conductor-backed ground coplanar waveguide having two ground planes, one on either side of said signal trace, wherein each of said ground planes is connected to said ground pad ring.
12. The semiconductor die of claim 11 , wherein said ground planes are connected to a backed conductor by a plurality of arrays.
13. The semiconductor die of claim 11 , wherein said conductor-backed ground coplanar waveguide extends along said signal trace into said ground pad ring to a point adjacent said signal pad.
14. The semiconductor of claim 11 , wherein said signal pad comprises two differential signal pads, wherein each of said differential signal pads is connected to said I/O cell by a signal trace, and wherein said signal traces extend between said ground planes.
15. A semiconductor die for use in flip chip applications comprising an array of I/O pads, said array comprising at least one signal pad and a plurality of non-signal pads, said plurality of non-signal pads being made up of ground pads and power pads, wherein said non-signal pads are positioned about said signal pad such that said signal pad is surrounded by an area of substantially constant DC potential, and wherein said signal pad is connected to an I/O cell by a signal trace.
16. The semiconductor die of claim 15 , wherein said signal pad comprises two differential signal pads and wherein each of said differential signal pads is connected to said I/O cell by a signal trace.
17. The semiconductor die of claim 15 , wherein the non-signal pads nearest said signal pad are ground pads.
18. The semiconductor die of claim 15 , wherein said non-signal pads are ground pads.
19. The semiconductor die of claim 15 , wherein said non-signal pads are power pads.
20. The semiconductor die of claim 17 , wherein said ground pads are connected to one another by a metal trace to form a ground pad ring.
21. The semiconductor die of claim 19 , wherein said power pads are connected to one another by a metal trace to form a power pad ring.
22. The semiconductor die of claim 20 , wherein said ground pad ring is connected to a conductor-backed ground coplanar waveguide, said conductor-backed ground coplanar waveguide having two ground planes, one on either side of said signal trace, wherein each of said ground planes is connected to said ground pad ring.
23. The semiconductor die of claim 22 , wherein said ground planes are connected to a backed conductor by a plurality of arrays.