Systems and methods for ESD protection
View Patent ↗A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.
1. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
two or more PMOS transistors arranged in series, the two or more PMOS transistors comprising at least a first PMOS transistor and a second PMOS transistor, the first PMOS transistor having a drain, a gate, and a source, the second PMOS transistor having a drain, a gate, and a source, wherein the drain of the first PMOS transistor is coupled to the anode of the diode, wherein the source of the second PMOS transistor is coupled to a first voltage reference terminal, wherein the source of the first PMOS transistor is coupled, directly or indirectly, to the drain of the second PMOS transistor, and wherein the gates of the PMOS transistors are coupled to voltage reference(s) so that at least one of the PMOS transistors is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
2. The integrated circuit of claim 1 , wherein the first voltage reference terminal is for ground.
3. The integrated circuit of claim 1 , wherein the source of the first PMOS transistor is coupled directly to the drain of the second PMOS transistor.
4. The integrated circuit of claim 1 , further comprising a third PMOS transistor, wherein the source of the first PMOS transistor is coupled indirectly to the drain of the second PMOS transistor via the third PMOS transistor in series between the first PMOS transistor and the second PMOS transistor, the third PMOS transistor having a gate, a drain, and a source, the drain of the third PMOS transistor coupled to the source of the first PMOS transistor, the source of the third PMOS transistor coupled to the drain of the second PMOS transistor.
5. The integrated circuit of claim 1 , further comprising a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate at least one output voltage between that of the node and the first voltage reference terminal as a reference voltage(s) for at least one of the PMOS transistors.
6. The integrated circuit of claim 5 , wherein the gate of the first PMOS transistor is coupled to the gate network, and wherein the gate of the second PMOS transistor is coupled to the source of the second PMOS transistor.
7. The integrated circuit of claim 5 , wherein the gate of the first PMOS transistor is coupled to the source of the first PMOS transistor, and wherein the gate of the second PMOS transistor is coupled to the gate network.
8. The integrated circuit of claim 5 , wherein the gates of both the first PMOS transistor and the second PMOS transistor are coupled to respective outputs of the gate network.
9. The integrated circuit of claim 5 , wherein the gate network comprises a voltage divider, and wherein the at least one output voltage is tapped from an inner terminal of the voltage divider.
10. The integrated circuit of claim 1 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
11. The integrated circuit of claim 1 , further comprising a diode group comprising a second diode and an NMOS transistor, the second diode having an anode and a cathode, the NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
12. The integrated circuit of claim 11 , wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
13. The integrated circuit of claim 1 , wherein the integrated circuit further comprises a deep Nwell for isolation of the cathode of the diode.
14. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the anode is coupled to a first voltage reference terminal; and
two or more PMOS transistors arranged in series, the two or more PMOS transistors comprising at least a first PMOS transistor and a second PMOS transistor, the first PMOS transistor having a drain, a gate, and a source, the second PMOS transistor having a drain, a gate, and a source, wherein the drain of the first PMOS transistor is coupled to the node, wherein the source of the second PMOS transistor is coupled to the cathode of the diode, wherein the source of the first PMOS transistor is coupled, directly or indirectly, to the drain of the second PMOS transistor, and wherein gates of the PMOS transistors are coupled to voltage reference(s) so that at least one of the PMOS transistors is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
15. The integrated circuit of claim 14 , wherein the first voltage reference terminal is for ground.
16. The integrated circuit of claim 14 , wherein the source of the first PMOS transistor is coupled directly to the drain of the second PMOS transistor.
17. The integrated circuit of claim 14 , further comprising a third PMOS transistor, wherein the source of the first PMOS transistor is coupled indirectly to the drain of the second PMOS transistor via the third PMOS transistor in series between the first PMOS transistor and the second PMOS transistor, the third PMOS transistor having a gate, a drain, and a source, the drain of the third PMOS transistor coupled to the source of the first PMOS transistor, the source of the third PMOS transistor coupled to the drain of the second PMOS transistor.
18. The integrated circuit of claim 14 , further comprising a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate at least one output voltage between that of the node and the first voltage reference terminal as a reference voltage(s) for at least one of the PMOS transistors.
19. The integrated circuit of claim 18 , wherein the gate of the first PMOS transistor is coupled to the gate network, and wherein the gate of the second PMOS transistor is coupled to the source of the second PMOS transistor.
20. The integrated circuit of claim 18 , wherein the gate of the first PMOS transistor is coupled to the source of the first PMOS transistor, and wherein the gate of the second PMOS transistor is coupled to the gate network.
21. The integrated circuit of claim 18 , wherein the gates of both the first PMOS transistor and the second PMOS transistor are coupled to respective outputs of the gate network.
22. The integrated circuit of claim 18 , wherein the gate of the first PMOS transistor is coupled to the gate network, and wherein the gate of the second PMOS transistor is coupled to the first voltage reference.
23. The integrated circuit of claim 18 , wherein the gate network comprises a voltage divider, and wherein the at least one output voltage is tapped from an inner terminal of the voltage divider.
24. The integrated circuit of claim 14 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
25. The integrated circuit of claim 14 , further comprising a diode group comprising a second diode and an NMOS transistor, the second diode having an anode and a cathode, the NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
26. The integrated circuit of claim 25 , wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
27. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the anode of the diode, wherein the source of the PMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the PMOS transistor is coupled to a reference voltage so that the PMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
28. The integrated circuit of claim 27 , wherein the gate of the PMOS transistor is coupled to the source of the PMOS transistor for the reference voltage.
29. The integrated circuit of claim 27 , further comprising a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate an output voltage between that of the node and the first voltage reference terminal, wherein the gate of the PMOS transistor is coupled to the output voltage of the gate network.
30. The integrated circuit of claim 27 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
31. The integrated circuit of claim 27 , further comprising a diode group comprising a second diode and an NMOS transistor, the second diode having an anode and a cathode, the NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
32. The integrated circuit of claim 31 , wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
33. The integrated circuit of claim 27 , wherein the integrated circuit further comprises a deep Nwell for isolation of the cathode of the diode.
34. The integrated circuit of claim 27 , wherein the PMOS transistor comprises a stack of PMOS transistors, wherein at least one of the PMOS transistors in the stack has a gate that is coupled to the output of the gate network.
35. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the anode is coupled to a first voltage reference terminal; and
a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the node, wherein the source of the PMOS transistor is coupled to the cathode of the diode, wherein the gate of the PMOS transistor is coupled to a reference voltage so that the PMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
36. The integrated circuit of claim 35 , wherein the gate of the PMOS transistor is coupled to the source of the PMOS transistor for the reference voltage.
37. The integrated circuit of claim 35 , further comprising a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate an output voltage between that of the node and the first voltage reference terminal, wherein the gate of the PMOS transistor is coupled to the output voltage of the gate network.
38. The integrated circuit of claim 35 , wherein the gate of the PMOS transistor is coupled to the first voltage reference terminal for the reference voltage.
39. The integrated circuit of claim 35 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
40. The integrated circuit of claim 35 , further comprising a diode group comprising a second diode and an NMOS transistor, the second diode having an anode and a cathode, the NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
41. The integrated circuit of claim 35 , wherein the PMOS transistor comprises a stack of PMOS transistors, wherein at least one of the PMOS transistors in the stack has a gate that is coupled to the output of the gate network.
42. The integrated circuit of claim 41 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
43. The integrated circuit of claim 41 , further comprising a diode group comprising a second diode and an NMOS transistor, the second diode having an anode and a cathode, the NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
44. The integrated circuit of claim 43 , wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
45. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
two or more NMOS transistors arranged in series, the two or more NMOS transistors comprising at least a first NMOS transistor and a second NMOS transistor, the first NMOS transistor having a drain, a gate, and a source, the second NMOS transistor having a drain, a gate, and a source, wherein the source of the first NMOS transistor is coupled to the anode of the diode, wherein the drain of the second NMOS transistor is coupled to a first voltage reference terminal, wherein the drain of the first NMOS transistor is coupled, directly or indirectly, to the source of the second NMOS transistor, and wherein gates of the NMOS transistors are coupled to voltage reference(s) so that at least one of the NMOS transistors is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
46. The integrated circuit of claim 45 , wherein the first voltage reference terminal is for ground.
47. The integrated circuit of claim 45 , wherein the drain of the first NMOS transistor is coupled directly to the source of the second NMOS transistor.
48. The integrated circuit of claim 45 , further comprising a third NMOS transistor, wherein the drain of the first NMOS transistor is coupled indirectly to the source of the second NMOS transistor via the third NMOS transistor in series between the first NMOS transistor and the second NMOS transistor, the third NMOS transistor having a gate, a drain, and a source, the source of the third NMOS transistor coupled to the drain of the first NMOS transistor, the drain of the third NMOS transistor coupled to the source of the second NMOS transistor.
49. The integrated circuit of claim 45 , further comprising a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate at least one output voltage between that of the node and the first voltage reference terminal as a reference voltage(s) for at least one of the NMOS transistors.
50. The integrated circuit of claim 49 , wherein the gate of the first NMOS transistor is coupled to the gate network, and wherein the gate of the second NMOS transistor is coupled to the source of the second NMOS transistor.
51. The integrated circuit of claim 49 , wherein the gate of the first NMOS transistor is coupled to the source of the first NMOS transistor, and wherein the gate of the second NMOS transistor is coupled to the gate network.
52. The integrated circuit of claim 49 , wherein the gate of the first NMOS transistor is coupled to the gate network, and wherein the gate of the second NMOS transistor is coupled to the gate network.
53. The integrated circuit of claim 49 , wherein the gate network comprises a voltage divider, and wherein the at least one output voltage is tapped from an inner terminal of the voltage divider.
54. The integrated circuit of claim 45 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
55. The integrated circuit of claim 45 , further comprising a diode group comprising a second diode and a third NMOS transistor, the second diode having an anode and a cathode, the third NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the third NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
56. The integrated circuit of claim 55 , wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
57. The integrated circuit of claim 45 , wherein the integrated circuit further comprises a deep Nwell for isolation of the cathode of the diode and for the two or more NMOS transistors.
58. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the first voltage reference terminal is for ground, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal.
59. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal;
wherein the gate of the NMOS transistor is coupled to the source of the NMOS transistor for the reference voltage.
60. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node;
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal; and
a gate network coupled to the node and to the first voltage reference terminal, wherein the gate network is configured to generate an output voltage between that of the node and the first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to the output voltage of the gate network.
61. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal;
wherein the NMOS transistor comprises a stack of NMOS transistors, wherein at least one of the NMOS transistors in the stack has a gate that is coupled to the output of the gate network.
62. The integrated circuit of claim 58 , further comprising a diode group comprising one or more diodes, the diode group having an anode and a cathode, wherein the anode is coupled to the node, wherein the cathode is coupled to a second voltage reference terminal that is intended to be at a higher voltage potential than a voltage of the first voltage reference terminal.
63. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node;
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal; and
a diode group comprising a second diode and a second NMOS transistor, the second diode having an anode and a cathode, the second NMOS transistor having a gate, a drain, and a source, wherein the anode is coupled to the node, wherein the cathode is coupled to the drain of the second NMOS transistor, and wherein the gate and the source are coupled to the first voltage reference terminal.
64. An integrated circuit with electrostatic discharge (ESD) protection, the integrated circuit comprising:
a node operatively coupled to a pad and to an operational circuit of the integrated circuit, wherein the operational circuit is to be protected from ESD;
a diode having an anode and a cathode, wherein the cathode is coupled to the node; and
an NMOS transistor having a gate, a drain, and a source, wherein the source of the NMOS transistor is coupled to the anode of the diode, wherein the drain of the NMOS transistor is coupled to a first voltage reference terminal, wherein the gate of the NMOS transistor is coupled to a reference voltage so that the NMOS transistor is “off” when voltage at the node is less than voltage at the first voltage reference terminal;
wherein the integrated circuit further comprises a deep Nwell for isolation of the cathode of the diode and for the two or more NMOS transistor.
65. The integrated circuit of claim 1 , wherein current for an ESD event is conducted through a bulk of a parasitic PNP bipolar transistor.
66. The integrated circuit of claim 14 , wherein current for an ESD event is conducted through a bulk of a parasitic PNP bipolar transistor.
67. The integrated circuit of claim 27 , wherein current for an ESD event is conducted through a bulk of a parasitic PNP bipolar transistor.
68. The integrated circuit of claim 35 , wherein current for an ESD event is conducted through a bulk of a parasitic PNP bipolar transistor.
69. The integrated circuit of claim 45 , wherein current for an ESD event is conducted through a bulk of a parasitic NPN bipolar transistor.
70. The integrated circuit of claim 58 , wherein current for an ESD event is conducted through a bulk of a parasitic NPN bipolar transistor.