Clock and data recovery locking technique for large frequency offsets
View Patent ↗Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.
1. An apparatus for recovering a clock signal, the apparatus comprising:
a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal; and
a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit takes into consideration whether the recovered clock signal is at least momentarily phase locked to the input data signal in selecting a frequency range, wherein the feedback circuit further comprises:
a phase tracking path; and
a frequency tracking path with an accumulator, the accumulator having at least one range limit that is dynamically selectable for dynamic selection of the limit of the frequency range of the feedback circuit, wherein the accumulator for the frequency tracking path is configured to have at least a first predetermined value range for a full range, a second predetermined value range for a first subrange, and a third predetermined value range for a second subrange, the second predetermined value range having a range different than the third predetermined value range, the second predetermined value range and the third predetermined value range having ranges smaller than the first predetermined value range, wherein the accumulator is initially configured to select the second predetermined value range, wherein the accumulator is configured to select the third predetermined value range after a predetermined time has elapsed after which phase lock has been determined to have not occurred, wherein the accumulator is further configured to select the first predetermined value range after phase lock has occurred.
2. An apparatus for recovering a clock signal, the apparatus comprising:
a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal; and
a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit takes into consideration whether the recovered clock signal is at least momentarily phase locked to the input data signal in selecting a frequency range, wherein the feedback circuit further comprises:
a phase tracking path; and
a frequency tracking path having an adjustable frequency tracking path gain, wherein the frequency tracking path has a first frequency tracking path gain when phase lock has not been determined and has a second frequency tracking path gain higher than the first frequency tracking path gain when phase lock has been determined, wherein the frequency tracking path is further configured to increase the frequency tracking path gain from the first frequency tracking path gain to the second frequency tracking path gain in an incremental manner such that the recovered clock signal remains within the locking range of the feedback circuit.
3. The apparatus as defined in claim 2 , wherein the apparatus is incorporated into a storage system.
4. A method for recovering a clock signal, the method comprising:
receiving an input data signal;
receiving a reference signal;
generating an adjustment for a recovered clock signal based at least partly on a comparison between the input data signal and a recovered clock signal;
limiting a frequency range for the adjustment to a first frequency range when the input data signal and the recovered clock signal are not locked;
limiting a frequency range for the adjustment to a second frequency range other than the first frequency range when the input data signal and the recovered clock signal are locked; and
generating the recovered clock signal based at least partly on the reference signal and the adjustment;
wherein limiting the frequency range for the adjustment to the first frequency range further comprises:
selecting one from a plurality of limited frequency ranges for the adjustment when the input data signal and the recovered clock signal are not locked, wherein each of the limited frequency ranges of the plurality has a frequency range that is smaller than the second frequency range, the plurality including the first frequency range;
determining whether the input data signal and the recovered clock signal have locked within a predetermined time interval for a particular frequency range from the plurality; and
selecting a different one from the plurality of limited frequency ranges at least partially in response to a determination that the predetermined time interval has elapsed without detection of phase lock;
wherein receiving the input data signal, receiving the reference signal, generating the adjustment, limiting the frequency range for the adjustment to the first frequency range, limiting the frequency range for the adjustment to the second frequency range, and generating the recovered clock signal are performed by electronic hardware.
5. The method as defined in claim 4 , wherein locked is phase locked.
6. The method as defined in claim 4 , wherein the second frequency range is larger than the first frequency range.
7. A method for recovering a clock signal, the method comprising:
receiving an input data signal;
receiving a reference signal;
generating an adjustment for a recovered clock signal based at least partly on a comparison between the input data signal and a recovered clock signal;
limiting a frequency range for the adjustment to a first frequency range when the input data signal and the recovered clock signal are not locked;
limiting a frequency range for the adjustment to a second frequency range other than the first frequency range when the input data signal and the recovered clock signal are locked;
generating the recovered clock signal based at least partly on the reference signal and the adjustment;
changing the limits for the frequency range for the adjustment by adjusting a frequency tracking path gain; and
adjusting the frequency tracking path gain from a gain corresponding to the first frequency range to a gain corresponding to the second frequency range in an incremental manner such that the recovered clock signal remains within a locking range of an associated phase tracking path;
wherein receiving the input data signal, receiving the reference signal, generating the adjustment, limiting the frequency range for the adjustment to the first frequency range, limiting the frequency range for the adjustment to the second frequency range, and generating the recovered clock signal are performed by electronic hardware.
8. The method as defined in claim 7 , wherein the second frequency range is larger than the first frequency range.
9. The method as defined in claim 7 , wherein locked is phase locked.