Systems and methods for actively-peaked current-mode logic
View Patent ↗A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.
1. A circuit fabricated in an integrated circuit with a differential input and a differential output, the circuit comprising:
a differential circuit with a first NMOS transistor and a second NMOS transistor, where the first NMOS transistor has a source, a gate, and a drain, and the second NMOS transistor has a source, a gate, and a drain, where the source of the first NMOS transistor and the source of the second NMOS transistor are coupled, where the gate of the first NMOS transistor and the gate of the second NMOS transistor are configured to receive the differential input, and where the drain of the first NMOS transistor and the drain of the second NMOS transistor are configured to provide the differential output;
a first current source with at least a first terminal, where the first terminal of the first current source is coupled to the source of the first NMOS transistor and to the source of the second NMOS transistor;
a first active load with at least a first terminal coupled to the drain of the first NMOS transistor of the differential circuit, where the first terminal of the first active load has an inductive impedance characteristic as seen from the drain of the first NMOS transistor; and
a second active load coupled to the drain of the second NMOS transistor of the differential circuit, where the second active load has an inductive impedance characteristic as seen from the drain of the second NMOS transistor;
wherein the differential circuit, the first current source, the first active load, and the second active load form at least part of a state machine.
2. The circuit as defined in claim 1 , where the first current source is an NMOS transistor with a source, a gate, and a drain, and where the first terminal of the first current source corresponds to the drain of the NMOS transistor.
3. The circuit as defined in claim 1 , wherein the first active load and the second active load exhibit the inductive impedance characteristic without benefit of a passive inductor.
4. The circuit as defined in claim 1 , wherein the first active load further comprises:
a third NMOS transistor with a source, a gate, and a drain, where the source corresponds to the first terminal of the first active load, where the drain is coupled to a first voltage reference; and
a resistance device with a first terminal and a second terminal, where the first terminal of the resistance device is coupled to the gate of the third NMOS transistor, and where the second terminal of the resistance device is coupled to a second voltage reference.
5. The circuit as defined in claim 4 , wherein the first active load further comprises a capacitor with a first terminal and a second terminal, where the first terminal of the capacitor is coupled to the gate of the third NMOS transistor, and where the second terminal of the capacitor is coupled to the source of the third NMOS transistor.
6. The circuit as defined in claim 4 , further comprising a delta-V GS bias that is coupled to the second voltage reference.
7. The circuit as defined in claim 4 , wherein the first active load corresponds to a tunable active load, and where the resistance device corresponds to a device with a controllable resistance.
8. The circuit as defined in claim 7 , wherein the resistance device corresponds to a fourth NMOS transistor with a source, a gate, and a drain, where the source of the fourth NMOS transistor corresponds to the first terminal of the resistance device, where the drain of the fourth NMOS transistor corresponds to the second terminal of the resistance device, and where the gate of the fourth NMOS transistor corresponds to a control terminal for the controllable resistance.
9. The circuit as defined in claim 4 , wherein the resistance device corresponds to a polysilicon resistor.
10. The circuit as defined in claim 1 , wherein the first active load further comprises:
a PMOS transistor with a source, a gate, and a drain, where the drain corresponds to the first terminal of the first active load, and where the source is coupled to a first voltage reference;
a resistance device with a first terminal and a second terminal, where the first terminal of the resistance device is coupled to the gate of the PMOS transistor, and where the second terminal of the resistance device is coupled to the drain of the PMOS transistor; and
a second current source with at least a first terminal coupled to the gate of the PMOS transistor and to the first terminal of the resistance device.
11. The circuit as defined in claim 10 , wherein the first active load further comprises a capacitor with a first terminal and a second terminal, where the first terminal of the capacitor is coupled to the gate of the PMOS transistor, and where the second terminal of the capacitor is coupled to the source of the PMOS transistor.
12. The circuit as defined in claim 1 , further comprising:
a second current source coupled to the drain of the first NMOS transistor of the differential circuit; and
a third current source coupled to the drain of the second NMOS transistor of the differential circuit.
13. The circuit as defined in claim 12 , wherein:
the second current source further comprises a first series combination of a first small NMOS transistor and a first large NMOS transistor, where the first small NMOS transistor is disposed in the current path between the drain of the first NMOS transistor and a drain of the first large NMOS transistor, where a gate of the first small NMOS transistor is coupled to a voltage reference, and where the first large NMOS transistor is configured as a current source; and
the third current source further comprises a second series combination of a second small NMOS transistor and a second large NMOS transistor, where the second small NMOS transistor is disposed in the current path between the drain of the second NMOS transistor and a drain of the second large NMOS transistor, where a gate of the second small NMOS transistor is coupled to a voltage reference, and where the second large NMOS transistor is configured as a current source.
14. The circuit as defined in claim 1 , further comprising:
a third NMOS transistor with a source, a gate, and a drain, where the drain of the third NMOS transistor is coupled to the drain of the first NMOS transistor, and where the gate of the third NMOS transistor is coupled to the gate of the first NMOS transistor;
a fourth NMOS transistor with a source, a gate, and a drain, where the drain of the fourth NMOS transistor is coupled to the drain of the second NMOS transistor, and where the gate of the fourth NMOS transistor is coupled to the gate of the second NMOS transistor;
at least one capacitive device with at least a first terminal and a second terminal, where the first terminal of the at least one capacitive device is coupled to the source of the third NMOS transistor, and where the second terminal of the at least one capacitive device is coupled to the source of the fourth NMOS transistor;
a second current source with at least a first terminal, where the first terminal of the second current source is coupled to the source of the third NMOS transistor and to the first terminal of the at least one capacitive device; and
a third current source with at least a first terminal, where the first terminal of the third current source is coupled to the source of the fourth NMOS transistor and to the second terminal of the at least one capacitive device.
15. The circuit as defined in claim 14 , wherein the at least one capacitive device corresponds to a capacitor with first terminal and a second terminal, where the first terminal of the capacitor corresponds to the first terminal of the at least one capacitive device and where the second terminal of the capacitor corresponds to the second terminal of the at least one capacitive device.
16. The circuit as defined in claim 14 , wherein the at least one capacitive device corresponds to a first capacitor with a first terminal and a second terminal and to a second capacitor with a first terminal and a second terminal, where the first terminal of the first capacitor corresponds to the first terminal of the at least one capacitive device, where the first terminal of the second capacitor corresponds to the second terminal of the at least one capacitive device, and where the second terminal of the first capacitor and the second terminal of the second capacitor are coupled to a voltage reference.
17. The circuit as defined in claim 16 , wherein the voltage reference is ground.
18. An integrated circuit with metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on a silicon substrate, the integrated circuit comprising:
a differential logic circuit implemented with current-controlled complementary metal-oxide semiconductor field-effect transistor circuits; and
active loads coupled to the transistor circuits of the differential logic circuit, where the active loads mimic the response of inductors without inclusion of an explicit inductor;
wherein the differential logic circuit and the active loads form at least part of a state machine.
19. The integrated circuit as defined in claim 18 , wherein the differential logic circuit is configured to correspond to at least a portion of a buffer, an inverter, an AND gate, a NAND gate, an OR gate, a NOR gate, a multiplexer, a latch, or a flip-flop.
20. The integrated circuit as defined in claim 18 , wherein the state machine is embodied in a microprocessor.
21. The integrated circuit as defined in claim 18 , wherein the state machine is embodied in a graphics processor.
22. The integrated circuit as defined in claim 18 , wherein the state machine is embodied in a serial-deserializer (SERDES).
23. The integrated circuit as defined in claim 18 , wherein the state machine comprises at least a combination of logic cells and a flip-flop.
24. The circuit as defined in claim 1 , wherein the state machine comprises at least a combination of logic cells and a flip-flop.