IP Library Granted Patent US 8,004,330
Granted Patent B1
US 8,004,330 · App. 12/627,345 · Granted Aug 23, 2011

Reduction of electromagnetic interference for differential signals

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Quick Facts
Patent No.
US 8,004,330
App. No.
12/627,345
Granted
Aug 23, 2011
Kind
B1
Abstract

Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cause electromagnetic interference (EMI), and are tightly regulated by appropriate agencies, such as the FCC. Common mode radiation from differential signals can also cause EMI. By modulating the slew rates of the rising and falling edges of the differential signal, and by applying negative feedback, symbol-rate related spurs can be spread over a wider frequency range than conventional spread spectrum clocking (SSC) techniques, and thus should generally be capable of greater EMI reduction than conventional SSC techniques.

Claims (38)

1. An apparatus for driving a differential signal, the apparatus comprising:

a first output node for a non-inverted output signal of a differential signal;

a second output node for an inverted output signal of the differential signal;

a first driver subcircuit having an output coupled to the first output node;

a second driver subcircuit having an output coupled to the second output node; and

a slew rate control circuit responsive to a slew rate control input to selectively activate transistors of the first driver subcircuit and the second driver subcircuit;

wherein in response to a first state of the slew rate control input, transitions at the first output node and the second output node have a first rising edge slew rate and a first falling edge slew rate, wherein the first rising edge slew rate is faster than the first falling edge slew rate;

wherein in response to a second state of the slew rate control input, transitions at the first output node and the second output node have a second rising edge slew rate and a second falling edge slew rate, wherein the second rising edge slew rate is slower than the second falling edge slew rate.

2. The apparatus of claim 1 , further comprising a modulator configured to select between the first state and the second state in a pseudo random manner.

3. The apparatus of claim 2 , wherein the modulator comprises a pseudo random binary sequence generator.

4. The apparatus of claim 2 , wherein the modulator comprises a delta sigma modulator.

5. The apparatus of claim 1 , further comprising a modulator configured to select between the first state and the second state in a pseudo random manner and in an open loop manner.

6. The apparatus of claim 1 , further comprising a modulator configured to select between the first state and the second state in a pseudo random manner and in a closed loop manner such that the probability of selecting one state versus the other varies depending upon a difference in a signal associated with a common mode signal detected during transitions of the differential signal.

7. The apparatus of claim 6 , wherein the signal associated with the common mode signal comprises a filtered gated common mode signal.

8. The apparatus of claim 1 , further comprising:

a mixer configured to mix a signal associated with a common mode signal with a data rate clock signal;

a low-pass filter configured to low pass filter an output of the mixer to generate a filtered down-converted common mode signal; and

a modulator configured to select between the first state and the second state in a pseudo random manner and in a closed loop manner such that the probability of selecting one state versus the other varies based at least partly on the filtered down-converted common mode signal.

9. A method of driving a differential signal, the method comprising:

driving a first output node for a non-inverted output signal of a differential signal with a first driver subcircuit;

driving a second output node for an inverted output signal of the differential signal with a second driver subcircuit;

receiving a slew rate control signal as an input; and

selectively activating transistors of the first driver subcircuit and the second driver subcircuit based at least partly on the slew rate control signal such that in response to a first state of the slew rate control input, transitions at the first output node and the second output node have a first rising edge slew rate and a first falling edge slew rate, wherein the first rising edge slew rate is faster than the first falling edge slew rate, and such that in response to a second state of the slew rate control input, transitions at the first output node and the second output node have a second rising edge slew rate and a second falling edge slew rate, wherein the second rising edge slew rate is slower than the second falling edge slew rate.

10. The method of claim 9 , further comprising modulating between the first state and the second state in a pseudo random manner.

11. The method of claim 10 , further comprising generating a pseudo random binary sequence for modulating.

12. The method of claim 9 , wherein modulating further comprises performing delta-sigma modulation.

13. The method of claim 9 , further comprising selecting between the first state and the second state in a pseudo random manner and in an open loop manner.

14. The method of claim 9 , further comprising selecting between the first state and the second state in a pseudo random manner and in a closed loop manner such that the probability of selecting one state versus the other varies depending upon a difference in a signal associated with a common mode signal detected during transitions of the differential signal.

15. The method of claim 14 , further comprises gating and filtering a common mode signal to generate the signal associated with the common mode signal.

16. The method of claim 9 , further comprising:

mixing a signal associated with a common mode signal with a data rate clock signal to generate a mixed signal;

low-pass filtering the mixed signal to generate a filtered down-converted common mode signal; and

selecting between the first state and the second state in a pseudo random manner and in a closed loop manner such that the probability of selecting one state versus the other varies based at least partly on the filtered down-converted common mode signal.

17. A method of compensating for process variations resulting in variability in slew rate, the method comprising:

observing slew rates of an output driver, wherein the output driver comprises a plurality of driver subcircuits, at least a portion of which can be selectively activated; and

selectively activating driver subcircuits of the plurality of driver subcircuits so that a rising edge slew rate approximately matches with a falling edge slew rate.

18. The method of claim 17 , further comprising exhaustively testing various combinations of driver subcircuits for slew rate.

19. The method of claim 17 , further comprising activating at least one driver subcircuit with a deliberately mismatch between its rising edge slew rate and its falling edge slew rate to compensate for variability of driver subcircuits in which mismatch is not intended.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
CHANGE OF NAME Recorded Apr 7, 2016
From: PMC-SIERRA, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 038381/0753 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: ACIMOVIC, PREDRAG; MISHRA, PARMANAND; HERNANDEZ, RICHARD WAYNE
To: PMC-SIERRA, INC.
Reel/Frame 023765/0151 →