Cyclic redundancy check circuit for use with self-synchronous scramblers
View Patent ↗The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.
1. A circuit for detecting and correcting errors in a bit stream, said circuit including at least two logical gates that determine if at least one of a plurality of conditions is present, each one of said plurality of conditions indicating at least one error in said bit stream and activation of at least one of said at least two logical gates changes a state of a specific bit in said bit stream to correct at least one error;
wherein each one of said plurality of conditions is a specific bit pattern denoting a unique error pattern in said bit stream, each bit in said specific bit pattern resulting from bitwise operations between specific selected bits in said bit stream;
wherein said plurality of conditions are divided into two groups, a first group which indicates a first type of error in said bit stream and a second group which indicates a second type of error in said bit stream; and
wherein said at least two logical gates include a first logic gate associated with said first group and a second logic gate associated with said second group, such that said first logic gate is activated if a bit error pattern from said first group is detected and said second logic gate is activated if a bit pattern from said second group is detected.
2. The circuit as claimed in claim 1 , wherein said first logic gate receives first logic gate inputs from bits resulting from bitwise operations dictated by a CRC polynomial between specific selected bits in said bit pattern, such that said first logic gate has a predetermined output when said first logic gate inputs correspond to a bit pattern chosen from a group consisting of: Syndrome A.
3. The circuit as claimed in claim 2 , wherein said predetermined output is a binary number.
4. The circuit as claimed in claim 1 , wherein said second logic gate receives second logic inputs from bits resulting from bitwise operations dictated by a CRC polynomial between specific selected bits in said bit pattern, such that said second logic gate has a predetermined output when said second logic inputs correspond to a bit pattern chosen from a group consisting of: Syndrome B.
5. The circuit as claimed in claim 4 , wherein said predetermined output is a binary number.
6. The circuit as claimed in claim 4 wherein said first logic gate and said second logic gate are both logical AND gates.
7. The circuit as claimed in claim 4 , wherein said first logic gate and said second logic gate are both logical OR gates.
8. The circuit as claimed in claim 4 , wherein said first logic gate and said second logic gate are both logical NAND gates.
9. The circuit as claimed in claim 4 , wherein said first logic gate and said second logic gate are both logical NOR gates.
10. The circuit as claimed in claim 4 , wherein said at least two logical gates includes an OR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
11. The circuit as claimed in claim 10 , wherein said first logic gate and said second logic gate are both logical AND gates.
12. The circuit as claimed in claims 4 , wherein said at least two logical gates includes an AND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
13. The circuit as claimed in claim 12 , wherein said first logic gate and said second logic gate are both logical OR gates.
14. The circuit as claimed in claim 4 , wherein said at least two logical gates includes a NAND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
15. The circuit as claimed in claim 14 , wherein said first logic gate and said second logic gate are both logical NAND gates.
16. The circuit as claimed in claim 4 , wherein said at least two logical gates includes a NOR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
17. The circuit as claimed in claim 16 , wherein said first logic gate and said second logic gate are both logical NOR gates.
18. The circuit as claimed in claim 1 wherein said first logic gate and said second logic gate are both logical AND gates.
19. The circuit as claimed in claim 1 , wherein said first logic gate and said second logic gate are both logical OR gates.
20. The circuit as claimed in claim 1 , wherein said first logic gate and said second logic gate are both logical NAND gates.
21. The circuit as claimed in claim 1 , wherein said first logic gate and said second logic gate are both logical NOR gates.
22. The circuit as claimed in claim 1 , wherein said at least two logical gates includes an OR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
23. The circuit as claimed in claim 22 , wherein said first logic gate and said second logic gate are both logical AND gates.
24. The circuit as claimed in claims 1 , wherein said at least two logical gates includes an AND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
25. The circuit as claimed in claim 24 , wherein said first logic gate and said second logic gate are both logical OR gates.
26. The circuit as claimed in claim 1 , wherein said at least two logical gates includes a NAND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
27. The circuit as claimed in claim 26 , wherein said first logic gate and said second logic gate are both logical NAND gates.
28. The circuit as claimed in claim 1 , wherein said at least two logical gates includes a NOR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
29. The circuit as claimed in claim 28 , wherein said first logic gate and said second logic gate are both logical NOR gates.
30. A circuit for detecting and correcting errors in a bit stream, said circuit including: at least two logical gates that determine if at least one of a plurality of conditions is present, each one of said plurality of conditions indicating at least one error in said bit stream and activation of at least one of said at least two logical gates changes a state of a specific bit in said bit stream to correct at least one error; said circuit being adapted to detect a condition caused by a single error that has passed through a self-synchronous descrambler to produce a multiplied error in said bit stream; wherein said at least two logical gates include a first logic gate associated with said first group and a second logic gate associated with said second group, such that said first logic gate is activated if a bit error pattern from said first group is detected and said second logic gate is activated if a bit pattern from said second group is detected.
31. The circuit as claimed in claim 30 , wherein said first logic gate receives first logic gate inputs from bits resulting from bitwise operations dictated by a CRC polynomial between specific selected bits in said bit pattern, such that said first logic gate has a predetermined output when said first logic gate inputs correspond to a bit pattern chosen from a group consisting of: Syndrome A.
32. The circuit as claimed in claim 31 , wherein said predetermined output is a binary number.
33. The circuit as claimed in claim 30 , wherein said second logic gate receives second logic inputs from bits resulting from bitwise operations dictated by a CRC polynomial between specific selected bits in said bit pattern, such that said second logic gate has a predetermined output when said second logic inputs correspond to a bit pattern chosen from a group consisting of: Syndrome B.
34. The circuit as claimed in claim 33 , wherein said predetermined output is a binary number.
35. The circuit as claimed in claim 33 wherein said first logic gate and said second logic gate are both logical AND gates.
36. The circuit as claimed in claim 33 , wherein said first logic gate and said second logic gate are both logical OR gates.
37. The circuit as claimed in claim 33 , wherein said first logic gate and said second logic gate are both logical NAND gates.
38. The circuit as claimed in claim 33 , wherein said first logic gate and said second logic gate are both logical NOR gates.
39. The circuit as claimed in claim 33 , wherein said at least two logical gates includes an OR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
40. The circuit as claimed in claim 39 , wherein said first logic gate and said second logic gate are both logical AND gates.
41. The circuit as claimed in claims 33 , wherein said at least two logical gates includes an AND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
42. The circuit as claimed in claim 41 , wherein said first logic gate and said second logic gate are both logical OR gates.
43. The circuit as claimed in claim 33 , wherein said at least two logical gates includes a NAND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
44. The circuit as claimed in claim 43 , wherein said first logic gate and said second logic gate are both logical NAND gates.
45. The circuit as claimed in claim 33 , wherein said at least two logical gates includes a NOR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
46. The circuit as claimed in claim 45 , wherein said first logic gate and said second logic gate are both logical NOR gates.
47. The circuit as claimed in claim 30 wherein said first logic gate and said second logic gate are both logical AND gates.
48. The circuit as claimed in claim 30 , wherein said first logic gate and said second logic gate are both logical OR gates.
49. The circuit as claimed in claim 30 , wherein said first logic gate and said second logic gate are both logical NAND gates.
50. The circuit as claimed in claim 30 , wherein said first logic gate and said second logic gate are both logical NOR gates.
51. The circuit as claimed in claim 30 , wherein said at least two logical gates includes an OR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
52. The circuit as claimed in claim 51 , wherein said first logic gate and said second logic gate are both logical AND gates.
53. The circuit as claimed in claims 30 , wherein said at least two logical gates includes an AND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
54. The circuit as claimed in claim 53 , wherein said first logic gate and said second logic gate are both logical OR gates.
55. The circuit as claimed in claim 30 , wherein said at least two logical gates includes a NAND gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
56. The circuit as claimed in claim 55 , wherein said first logic gate and said second logic gate are both logical NAND gates.
57. The circuit as claimed in claim 30 , wherein said at least two logical gates includes a NOR gate receiving an input from said first logic gate and said second logic gate such that a state of a specific bit in said bit pattern is changed if either said first logic gate or said second logic gate is activated.
58. The circuit as claimed in claim 57 , wherein said first logic gate and said second logic gate are both logical NOR gates.