Clock and data recovery locking technique for large frequency offsets
View Patent ↗Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.
1. An apparatus for recovering a clock signal, the apparatus comprising:
a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal;
a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit is configured to select a first locking range when phase lock has not been detected, wherein the first locking range is less than a frequency modulation associated with the input data signal, and being configured to select a second locking range broader than the first locking range when phase lock between the recovered clock signal and the input data signal has at least momentarily been detected, wherein the second locking range is sufficient to sustain lock to the input data signal over a full cycle of the frequency modulation associated with the input data signal, wherein the feedback circuit generates the recovered clock signal in a phase-locked manner while operating with the second locking range;
a phase tracking path; and
a frequency tracking path with an accumulator, the accumulator having at least one range limit that is dynamically selectable for dynamic selection of the limit of the locking range of the feedback circuit.
2. The apparatus as defined in claim 1 , wherein the apparatus is incorporated into a storage system.
3. An apparatus for recovering a clock signal, the apparatus comprising:
a phase detector configured to receive an input data signal and to receive a recovered clock signal, the phase detector further configured to generate a signal with an indication of a phase difference between the input data signal and the recovered clock signal;
a feedback circuit operatively coupled to the phase detector, the feedback circuit configured to receive the generated signal from the phase detector and to receive a reference signal, the feedback circuit configured to generate the recovered clock signal, wherein the feedback circuit is configured to select a first locking range when phase lock has not been detected, wherein the first locking range is less than a frequency modulation associated with the input data signal, and being configured to select a second locking range broader than the first locking range when phase lock between the recovered clock signal and the input data signal has at least momentarily been detected, wherein the second locking range is sufficient to sustain lock to the input data signal over a full cycle of the frequency modulation associated with the input data signal, wherein the feedback circuit generates the recovered clock signal in a phase-locked manner while operating with the second locking range;
a phase tracking path; and
a frequency tracking path having an adjustable frequency tracking path gain, wherein the frequency tracking path has a first frequency tracking path gain when phase lock has not been determined and has a second frequency tracking path gain higher than the first frequency tracking path gain when phase lock has been determined.
4. The apparatus as defined in claim 1 , wherein the apparatus is incorporated into a storage system.
5. An apparatus for recovering a clock signal, the apparatus comprising:
means for receiving an input data signal;
means for generating a recovered clock signal based at least partially on a reference signal and an adjustment;
means for generating the adjustment for the recovered clock signal based at least partly on a comparison between the input data signal and the recovered clock signal; and
means for limiting a frequency range of the adjustment to a first locking range when the input data signal and the recovered clock signal are not locked and for limiting a frequency range of the adjustment to a second locking range broader than the first locking range when phase lock between the input data signal and the recovered clock signal has at least momentarily been detected, wherein the second locking range is sufficient to sustain lock to the input data signal over a full cycle of the frequency modulation associated with the input data signal, wherein the feedback circuit generates the recovered clock signal in a phase-locked manner while operating with the second locking range;
wherein the input data receiving means comprises a phase detector, the reference signal generating means comprises a phase rotator, the adjustment generating means comprises an accumulator range controller, and the frequency range limiting means comprises at least a phase tracking path and a frequency tracking path.
6. The apparatus as defined in claim 5 , further comprising changing the limits for the frequency range of the adjustment by adjusting a frequency tracking path gain.
7. The apparatus as defined in claim 5 , wherein the apparatus is incorporated into a storage system.
8. The apparatus as defined in claim 5 , wherein the apparatus is incorporated into a storage system.
9. A method for recovering a clock signal, the method comprising:
receiving an input data signal;
receiving a reference signal;
generating an adjustment for a recovered clock signal based at least partly on a comparison between the input data signal and a recovered clock signal;
limiting a frequency range for the adjustment to a first locking range when the input data signal and the recovered clock signal are not locked;
limiting a frequency range for the adjustment to a second locking range broader than the first locking range when phase lock between the input data signal and the recovered clock signal has at least momentarily been detected, wherein the second locking range is sufficient to sustain lock to the input data signal over a full cycle of the frequency modulation associated with the input data signal; and
generating the recovered clock signal based at least partly on the reference signal and the adjustment, wherein the recovered clock signal is generated in a phase-locked manner while operating with the second locking range;
wherein receiving the input data signal, receiving the reference signal, generating the adjustment, limiting the frequency range for the adjustment to the first frequency range, limiting the frequency range for the adjustment to the second frequency range, and generating the recovered clock signal are performed by electronic hardware.
10. The method as defined in claim 9 , further comprising dynamically changing a range limit of an accumulator associated with the adjustment to change a locking range for the adjustment.
11. The method as defined in claim 9 , further comprising changing the limits for the locking range for the adjustment by adjusting a frequency tracking path gain.
12. The method as defined in claim 9 , wherein locked is phase locked.