Phase-locked loop based clock generator and method for operating same
View Patent ↗An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.
1. An integer-N phase-locked loop clock generator, where N is a positive integer, comprising:
a reference clock;
a first phase generator for generating N first phase signals from a signal from the reference clock;
a voltage controlled oscillator;
a clock divider for dividing down a signal from the voltage controlled oscillator;
a second phase generator for generating N second phase signals from the divided down voltage controlled oscillator signal;
a mapper configured to receive N phase pairs and output the N phase pairs as M phase pairs, where M is a positive integer greater than N, each of the N phase pairs comprising a respective one of the N first phase signals generated by the first phase generator and a respective one of the N second phase signals generated by the second phase generator;
M phase frequency detectors, each phase frequency detector configured to receive a respective one of the M phase pairs, and to generate a pulse signal based on a comparison of the first phase signal with the second phase signal of the respective received phase pair;
M charge pumps, each charge pump configured to receive the pulse signal generated by a respective one of the M phase frequency detectors and to generate a control current based on the received pulse signal; and
a loop filter for receiving the control current from each of the M charge pumps and for controlling the voltage controlled oscillator based on the received control currents.
2. The integer-N phase-locked loop clock generator of claim 1 , wherein each of the M phase frequency detectors is configured to compare a phase of the first phase signal with a phase of the second phase signal of the respective received phase pair and to generate the pulse signal when the phase of the first phase signal is unaligned with the phase of the second phase signal.
3. The integer-N phase-locked loop clock generator of claim 1 , wherein the clock divider divides the signal from the voltage controlled oscillator by N.
4. The integer-N phase-locked loop clock generator of claim 1 , wherein each of the M phase frequency detectors is configured to compare a frequency of the first phase signal with a frequency of the second phase signal of the respective received phase pair and to generate the pulse signal when the frequency of the first phase signal is different than the frequency of the second phase signal.
5. The integer-N phase-locked loop clock generator of claim 4 , wherein each of the M phase frequency detectors is configured to compare a phase of the first phase signal with a phase of the second phase signal of the respective received phase pair, to compare a frequency of the first phase signal with a frequency of the second phase signal of the respective received phase pair, and to generate the pulse signal when both the phase of the first phase signal is unaligned with the phase of the second phase signal and the frequency of the first phase signal is different than the frequency of the second phase signal.
6. The integer-N phase-locked loop clock generator of claim 1 , wherein the first phase generator is the identical to the second phase generator, to introduce identical errors in spacing a phase of the first N phase signals and the second N phase signals, and to reduce unnecessary activation of the M phase frequency detectors and the M charge pumps.
7. The integer-N phase-locked loop clock generator of claim 1 , wherein the mapper outputs at least one of the N phase pairs to two or more of the M phase frequency detectors.
8. The integer-N phase-locked loop clock generator of claim 1 , wherein the mapper maps phase pair X of N to phase frequency detector D of M, according to the following:
D=X+N *(0 to DIV( M,N )−1), wherein
X is a positive integer number between 1 and N, each X corresponding to only one of the N phase pairs;
DIV(M,N) is equal to the quotient of M divided by N, namely, the number of times N divides completely into M; and
D is a positive integer number between 1 and M, each D corresponding to only one of the phase frequency detectors.
9. A method of controlling a frequency of an output clock signal, comprising
generating a reference clock signal;
generating N first phase signals from the reference clock signal;
dividing down the output clock signal;
generating N second phase signals from the divided down output clock signal;
mapping N phase pairs to M phase pairs, where M is a positive integer greater than N, each N phase pair comprising a respective one of the N first phase signals and a respective one of the N second phase signals;
generating M pulse signals, each of the M pulse signals being generated based on a comparison of the first phase signal with the second phase signal of a respective one of the M phase pairs;
generating M control currents based on the M pulse signals; and
changing the frequency of the output clock signal based on the M control currents.
10. The method of claim 9 , wherein each of the M pulse signals is generated when a phase of the first phase signal is unaligned with a phase of the second phase signal.
11. The method of claim 9 , wherein dividing down the output clock signal comprises dividing down-the output clock signal by a factor of N.
12. The method of claim 9 , wherein each of the M pulse signals is generated when a frequency of the first phase signal is different than a frequency of the second phase signal.
13. The method of claim 9 , wherein, each of the M pulse signals is generated when both a phase of the first phase signal is unaligned with a phase of the second phase signal and when frequency of the first phase signal is different than a frequency of the second phase signal.
14. The method of claim 9 , wherein mapping N phase pairs to M phase pairs comprises mapping at least one of the N phase pairs to two or more of the M phase pairs.
15. The method of claim 9 , wherein mapping N phase pairs to M phase pairs comprises mapping phase pair X to phase pair D, according to the following:
D=X+N *(0 to DIV( M,N )−1), wherein
X is a positive integer number between 1 and N, each X corresponding to only one of the N phase pairs;
DIV(M,N) is equal to the quotient of M divided by N, namely, the number of times N divides completely into M; and
D is a positive integer number between 1 and M, each D corresponding to only one of the phase frequency detectors.
16. An integer-N phase-locked loop clock generator, where N is a positive integer, comprising:
a reference clock;
a first phase generator for generating a plurality of phases of a signal from the reference clock;
a voltage controlled oscillator;
a clock divider for dividing down a signal from the voltage controlled oscillator;
a second phase generator for generating a plurality of phases of the divided down voltage controlled oscillator signal;
a plurality of phase frequency detectors for comparing a plurality of phase pairs and generating a pulse signal, each pair comprising one of the plurality of phases of the first phase generator and one of the plurality of phases of the second phase generator; and
a plurality of charge pumps for controlling the voltage controlled oscillator based on the pulse signal;
a mapper for mapping the plurality phase pairs to the plurality of phase frequency detectors;
wherein the mapper maps phase pair X to phase frequency detector D, according to the following:
D=X+N *(0 to DIV( M,N )−1), wherein
M is the total number of phase frequency detectors;
N is the total number of phase pairs of the first phase generator and the second phase generator;
X is a positive integer number between 1 and N, each X corresponding to only one of the plurality of phase pairs of the first phase generator and the second phase generator;
DIV(M,N) is equal to the quotient of M divided by N, namely, the number of times N divides completely into M; and
D is a positive integer number between 1 and M, each D corresponding to only one of the phase frequency detectors.
17. The integer-N phase-locked loop clock generator of claim 16 , wherein the phase frequency detectors generate the pulse signal when either or both of the phase and the frequency of any of the phase pairs are not the same.
18. The integer-N phase-locked loop clock generator of claim 16 , wherein the clock divider divides the signal from the voltage controlled oscillator by N.
19. The integer-N phase-locked loop clock generator of claim 16 , wherein the mapper maps at least one of the plurality of phase pairs to two or more of the phase frequency detectors.
20. The integer-N phase-locked loop clock generator of claim 18 , wherein the first phase generator generates N phases of the signal from the reference clock, and the second phase generator generates N phases of the divided down signal from the voltage controlled oscillator, and wherein the integer-N phase-locked loop clock generator further comprises at least N phase frequency detectors and at least N charge pumps.