Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper
View Patent ↗The invention provides a synchronizer incorporating a Δ-Σ modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the Δ-Σ modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block's frequency. A mapper incorporating the Δ-Σ modulator interprets the pulse train output by the Δ-Σ modulator as stuff/null/de-stuff commands.
1. A signal synchronization mapper, for mapping an input data stream characterized by a first frequency into an output data stream characterized by a second frequency, said mapper comprising:
(a) a frequency offset measurement block for producing a frequency offset output signal representative of frequency offset between:
(i) a recovered clock signal representative of the frequency of said input data stream;
(ii) a reference clock signal;
(b) a frequency-locked loop coupled to receive and reduce jitter in said frequency offset output signal, and for producing a jitter-reduced output signal; and,
(c) a Δ-Σ modulator external to and series-connected to said frequency-locked loop to receive and quantize said jitter-reduced output signal and for producing one of a preselected number of bit stuffing signals;
(d) a FIFO buffer coupled between said input and output data streams; and
(e) a FIFO adjuster coupled between said FIFO buffer and said frequency-locked loop, said FIFO adjuster for synchronizing said frequency-locked loop with said FIFO buffer;
wherein:
(f) said frequency offset measurement block operates at a measurement frequency;
(g) said Δ-Σ modulator operates at a stuffing frequency; and,
(h) said measurement frequency is not equal to said stuffing frequency.
2. A signal synchronization mapper as defined in claim 1 , wherein said measurement frequency is greater than said stuffing frequency.
3. A signal synchronization mapper for mapping an input data stream characterized by a first frequency into an output data stream characterized by a second frequency, said mapper comprising:
(a) a frequency offset measurement block for producing a frequency offset output signal representative of frequency offset between:
(i) a recovered clock signal representative of the frequency of said input data stream;
(ii) a reference clock signal;
(b) a frequency-locked loop coupled to receive and reduce jitter in said frequency offset output signal, and for producing a jitter-reduced output signal; and,
(c) a Δ-Σ modulator external to and series-connected to said frequency-locked loop to receive and quantize said jitter-reduced output signal and for producing one of a preselected number of bit stuffing signals;
(d) a FIFO buffer coupled between said input and output data streams;
(e) a FIFO adjuster coupled between said FIFO buffer and said frequency-locked loop, said FIFO adjuster for synchronizing said frequency-locked loop with said FIFO buffer;
(f) an adder having:
(i) a first input coupled to receive said frequency offset measurement block output signal;
(ii) a second input coupled to receive an output signal produced by said FIFO adjuster;
(iii) an output coupled to an input of said frequency-locked loop;
(g) said frequency-locked loop having an output coupled to an input of said Δ-Σ modulator; and,
(h) said Δ-Σ modulator having an output coupled to a timing controller for producing stuff, null or destuff commands corresponding to said respective bit stuffing signals.
4. A signal synchronization mapper as defined in claim 3 , wherein said Δ-Σ modulator further comprises a multiplier having a multiplication factor M, said multiplier coupled between said Δ-Σ modulator input and said Δ-Σ modulator output.
5. A signal synchronization mapper as defined in claim 4 , wherein;
(a) said Δ-Σ modulator further comprises a tri-level quantizer for producing said bit stuffing signals; and,
(b) said bit stuffing signals each further comprise a single bit stuff/destuff indicator for each bit stuff/destuff opportunity defined by a protocol characterizing data communication via said input and output data streams.
6. A signal synchronization mapper as defined in claim 5 , wherein:
(a) said quantizer has a threshold characteristic ±[(M/2)+K s ], where K s is a pre-defined constant;
(b) said bit stuff/destuff indicator further comprises:
(1) −1 when signals input to said quantizer are less than −[(M/2)+K s ];
(ii) 0 when signals input to said quantizer are between −[(M/2)+K s ] and +[(M/2)+K s ]; and,
(iii) +1 when signals input to said quantizer are greater than +[(M/2)+K s ].
7. A signal synchronization mapper as defined in claim 4 , wherein:
(a) said Δ-Σ modulator further comprises a multi-level quantizer for producing said bit stuffing signals; and,
(b) said bit stuffing signals further comprise a plurality of bit stuff/destuff indicators for each stuff/destuff opportunity defined by a protocol characterizing data communication via said input and output data streams.
8. A signal synchronization mapper for mapping an input data stream characterized by a first frequency into an output data stream characterized by a second frequency, said mapper comprising:
(a) a frequency offset measurement block for producing a frequency offset output signal representative of frequency offset between:
(i) a recovered clock signal representative of the frequency of said input data stream;
(ii) a reference clock signal;
(b) a frequency-locked loop coupled to receive and reduce jitter in said frequency offset output signal, and for producing a jitter-reduced output signal; and,
(c) a Δ-Σ modulator external to and series-connected to said frequency-locked loop to receive and quantize said jitter-reduced output signal and for producing one of a preselected number of bit stuffing signals;
(d) a FIFO buffer coupled between said input and output data streams;
(e) a FIFO adjuster coupled between said FIFO buffer and said frequency-locked loop, said FIFO adjuster for synchronizing said frequency-locked loop with said FIFO buffer;
said frequency-locked loop further comprising:
(f) a first adder for adding a first feedback signal to said frequency offset output signal to produce a first adder output signal;
(g) a second adder for adding a second feedback signal to said first adder output signal to produce a second adder output signal;
(h) an amplifier for amplifying said second adder output signal;
(i) a downsampler for synchronizing said frequency-locked loop and said Δ-Σ modulator;
(j) a first delay element coupled between an output of said downsampler and an input of said first adder, said first delay element for producing said first feedback signal; and,
(k) a second delay element coupled between an output of said second adder and an input of said second adder, said second delay element for producing said second feedback signal.
9. A signal synchronization mapper for mapping an input data stream characterized by a first frequency into an output data stream characterized by a second frequency said mapper comprising:
(a) a frequency offset measurement block for producing a frequency offset output signal representative of frequency offset between:
(i) a recovered clock signal representative of the frequency of said input data stream;
(ii) a reference clock signal;
(b) a frequency-locked loop coupled to receive and reduce jitter in said frequency offset output signal, and for producing a jitter-reduced output signal; and,
(c) a Δ-Σ modulator external to and series-connected to said frequency-locked loop to receive and quantize said jitter-reduced output signal and for producing one of a preselected number of bit stuffing signals;
(d) a FIFO buffer coupled between said input and output data streams;
(e) a FIFO adjuster coupled between said FIFO buffer and said frequency-locked loop, said FIFO adjuster for synchronizing said frequency-locked loop with said FIFO buffer:
said Δ-Σ modulator further comprising:
(f) a subtracter for subtracting a first feedback signal from said jitter-reduced output signal to produce a val output signal;
(g) a first adder for adding said val output signal to an A0 feedback signal to produce a val+A0 output signal;
(h) a second adder for adding said val+A0 output signal to an A1 feedback signal to produce a val+A0+A1 output signal;
(i) a third adder for adding said val+A0 output signal to said val+A0+A1 output signal to produce a 2val+2A0+A1 output signal;
(j) a first delay element coupled between an output of said first adder and an input of said first adder, said first delay element for producing said A0 feedback signal;
(k) a second delay element coupled between an output of said second adder and an input of said second adder, said second delay element for producing said A1 feedback signal;
(l) a quantizer coupled to receive said 2val+2A0+A1 output signal, said quantizer for producing said bit stuffing signals;
(m) a third delay element coupled to an output of said quantizer, said third delay element for producing phase increment and phase decrement signals corresponding to said bit stuffing signals; and,
(n) a multiplier coupled between an output of said third delay element and an input of said subtracter, said multiplied for multiplying said phase increment and phase decrement signals by a factor M.