System and method for split ring first in first out buffer memory with priority

1. A buffer memory system, comprising:

a buffer memory residing in a fast pattern processor of a network device, the buffer memory including a plurality of memory locations for storage; and

a controller configured to

control the storage and retrieval of data from the plurality of memory locations,

allocate a first portion of the plurality of memory locations of the buffer memory to a first buffer, wherein the remaining portion of the plurality of memory locations define a second portion;

allocate a portion of the second portion to a second buffer and the remaining portion of the second portion defines a third portion, wherein the first buffer and the second buffer are arranged as a ring buffer;

reserve a portion of the third portion for assignment to the second butler, with the second buffer assigned a higher priority over the first buffer; and

selectively allocate remaining one or more memory locations of the third portion to the first buffer or to the second buffer by retaining ring buffer structure of the first buffer and the second buffer where an allocated first memory location follows an allocated last memory location in each of the first buffer and the second buffer.

2. The buffer memory system of claim 1 , wherein the stored locations of the second buffer are preferentially read over the stored locations of the first buffer.

3. The buffer memory system of claim 2 , wherein the first buffer is assigned to store data from a first input data stream and the second buffer is assigned to store data from a second input data stream.

4. The buffer memory system of claim 3 , wherein the second input data stream is based on an IEEE 1588 protocol.

5. The buffer memory system of claim 3 , wherein the fast input data stream and the second input data stream are received by a physical interface of a network device, before being processed by the controller.

6. The buffer memory system of claim 5 , wherein the controller is part of the fast pattern processor of the network device.

7. A method for allocating memory locations in a buffer memory system, comprising:

providing a buffer memory with a plurality of memory locations for storage. wherein the buffer memory is a part of a fast pattern processor of a network device:

allocating a first portion of the plurality of memory locations to a first buffer, wherein the remaining portion of the plurality of memory locations defines a second portion;

allocating a portion of the second portion to a second buffer, the remaining portion of the second portion defining a third portion available for allocation to either the first buffer or the second buffer, wherein the first buffer and the second buffer are arranged as a ring buffer;

reserving a portion of the third portion for assignment to the second buffer, with the second buffer assigned a higher priority over the first buffer: and

selectively assigning remaining one or more of the memory locations of the third portion to the first buffer or to the second buffer by retaining ring buffer structure of the first buffer and the second buffer where an allocated first memory location follows an allocated last memory location in each of the first buffer and the second buffer.

8. The method of claim 7 , further including assigning the first buffer to store data from a first input data stream and assigning the second buffer to store data from a second input data stream.

9. The method of claim 8 , wherein the second input data stream is based on an IEEE 1588 protocol.

10. The method of claim 8 , wherein the stored data in the second buffer is preferentially read over the first buffer.

11. The method of claim 8 , wherein the first input data stream and the second input data stream are received by a physical interface of a network device, before storing data in the first buffer and the second buffer.

12. A non-transitory computer readable storage medium having instructions that, when executed by a computing device causes the computing device to:

provide a buffer memory with a plurality of memory locations for storage, wherein the buffer memory is a part a fast pattern processor of a network device;

allocate a first portion of the plurality of memory locations to a first buffer, wherein the remaining portion of the plurality of memory locations defines a second portion:

allocate a portion of the second portion to a second buffer. the remaining portion of the second portion defining a third portion available for allocation to either the first buffer or the second buffer, wherein the first buffer and the second buffer are arranged as a ring buffer;

reserve a portion of the third portion for assignment to the second buffer, with the second buffer assigned a higher priority over the first buffer; and

selectively assign remaining one or more of the memory locations of the third portion to the fast buffer or to the second buffer by retaining ring buffer structure of the first buffer and the second buffer where an allocated first memory location follows an allocated last memory location in each of the first buffer and the second buffer.