IP Library Granted Patent US 8,352,669
Granted Patent B2
US 8,352,669 · App. 12/430,438 · Granted Jan 8, 2013

Buffered crossbar switch system

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Quick Facts
Patent No.
US 8,352,669
App. No.
12/430,438
Granted
Jan 8, 2013
Kind
B2
Abstract

Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an N i -input by M i -output switch fabric, wherein N i and M i are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.

Claims (35)

1. Apparatus for transferring data between data modules, each of said data modules being at least one of a data processing module and a data storage module, the apparatus comprising:

at least one pair of crossbar switches, wherein input nodes and output nodes of each of the crossbar switches are coupled to corresponding ones of the data modules, a first crossbar switch having an N-input node by M-output node switch fabric, and a second crossbar switch having an M-input node by N-output node switch fabric, where N and M are each positive integers greater than one, wherein N and M are not equal, and wherein each crossbar switch comprises:

an input buffer at each input node having an input arbiter configured to read data packets from each input node to one or more corresponding crosspoint buffers in accordance with a first scheduling algorithm;

one crosspoint buffer at each crosspoint of the switch fabric, the crosspoint buffer providing a queue having an output arbiter configured to read data packets from the crosspoint buffer queue to an output node corresponding to the crosspoint buffer in accordance with a second scheduling algorithm, wherein, for each crosspoint buffer queue a depth of the queue varies in accordance with a round-trip time of data transfer through the at least one pair of crossbar switches; and

each output node configured to receive segments of data packets provided from one or more corresponding crosspoint buffers,

wherein, when a data storage module employs sequential addressing of locations in memory, addresses of the locations in memory are scrambled before passing the data through the at least one crossbar switch, and

wherein the first crossbar switch directs data from a group of data processing modules to a group of data storage modules, the second crossbar switch directs data from the data storage modules to the data processing modules, each data processing module has a first arbiter that controls a data processing module to transfer data to the input node of the first crossbar switch, and each data storage module has a second arbiter that controls a data memory controller to transfer data to the input node of the second crossbar switch.

2. The invention as recited in claim 1 , further comprising an output buffer at each output node, the output buffer configured to store segments of data packets provided from one or more corresponding crosspoint buffers.

3. The invention as recited in claim 1 , wherein the input buffer at each input node further comprises one of: a first-in, first-out (FIFO) buffer, a virtual output queue (VOQ), or a push-in, first-out buffer (FIFO).

4. The invention as recited in claim 1 , wherein at least one of the first scheduling algorithm and the second scheduling algorithm use a round-robin scheduling algorithm.

5. The invention as recited in claim 4 , wherein the round-robin scheduling algorithm of at least one of the first scheduling algorithm and the second scheduling algorithm employs priority delivery for one or more data processing modules.

6. The invention as recited in claim 1 , wherein the N-input node by M-output node switch fabric comprises M inter-coupled N-to-1 multiplexers.

7. The invention as recited in claim 1 , wherein, the packet of data provided to the input buffer is partitioned into equal length cells.

8. The invention as recited in claim 7 , wherein the input buffer is a first-in, first-out (FIFO) buffer.

9. The invention as recited in claim 1 , wherein, the apparatus is implemented in a monolithic integrated circuit chip.

10. The invention as recited in claim 1 , wherein the apparatus comprises at least five crossbar switches: a first crossbar switch for transfer of address data from a data processing module to a data storage module, a second crossbar switch for transfer of user data from the data processing module to the data storage module, a third crossbar switch for transfer of address data from the data storage module to the data processing module, a fourth crossbar switch for transfer of user data from the data storage module to the data processing module, and a fifth crossbar switch for transfer of responses from the data storage module to the data processing module.

11. A method of transferring data between data modules, each of said data modules being at least one of a data processing module and a data storage module, the method comprising:

scrambling, when a data storage module employs sequential addressing of locations in memory, addresses of the locations in memory;

passing the data through at least one pair of crossbar switches, wherein input nodes and output nodes of each of the crossbar switches are coupled to corresponding ones of the data modules, a first crossbar switch having an N-input node by M-output node switch fabric, and a second crossbar switch having an M-input node by N-output node switch fabric, where N and M are each positive integers greater than one, wherein N and M are not equal,

directing, by the first crossbar switch, data from a group of data processing modules to a group of data storage modules, and directing, by the second crossbar switch, data from the data storage modules to the data processing modules, wherein each data processing module has a first arbiter that controls a data processing module to transfer data to the input node of the first crossbar switch, and each data storage module has a second arbiter that controls a data memory controller to transfer data to the input node of the second crossbar switch;

wherein each crossbar switch performs the steps of:

reading, from an input buffer at each input node having an input arbiter, data packets from each input node to one or more corresponding crosspoint buffers in accordance with a first scheduling algorithm;

reading, from an output arbiter of a crosspoint buffer at each crosspoint of the switch fabric, the crosspoint buffer having a queue with an output arbiter, data packets from the crosspoint buffer queue to an output node corresponding to the crosspoint buffer in accordance with a second scheduling algorithm;

varying, for each crosspoint buffer queue a depth of the queue in accordance with a round-trip time of data transfer through the at least one pair of crossbar switches; and

receiving, at an output node, segments of data packets from one or more corresponding crosspoint buffers.

12. The invention as recited in claim 11 , further comprising partitioning the packet of data provided to the input buffer into equal length cells.

13. A machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for transferring data between data modules, each of said data modules being at least one of a data processing module and a data storage module, comprising the steps of:

scrambling, when a data storage module employs sequential addressing of locations in memory, addresses of the locations in memory;

passing the data through at least one pair of crossbar switches, wherein input nodes and output nodes of each of the crossbar switches are coupled to corresponding ones of the data modules, a first crossbar switch having an N-input node by M-output node switch fabric, and a second crossbar switch having an M-input node by N-output node switch fabric, where N and M are each positive integers greater than one, wherein N and M are not equal,

directing, by the first crossbar switch, data from a group of data processing modules to a group of data storage modules, and directing, by the second crossbar switch, data from the data storage modules to the data processing modules, each data processing module has a first arbiter that controls a data processing module to transfer data to the input node of the first crossbar switch, and each data storage module has a second arbiter that controls a data memory controller to transfer data to the input node of the second crossbar switch;

wherein each crossbar switch performs the steps of:

reading, from an input buffer at each input node having an input arbiter, data packets from each input node to one or more corresponding crosspoint buffers in accordance with a first scheduling algorithm;

reading, from an output arbiter of a crosspoint buffer at each crosspoint of the switch fabric, the crosspoint buffer having a queue with an output arbiter, data packets from the crosspoint buffer queue to an output node corresponding to the crosspoint buffer in accordance with a second scheduling algorithm;

varying, for each crosspoint buffer queue a depth of the queue in accordance with a round-trip time of data transfer through the at least one pair of crossbar switches; and

receiving, at an output node, segments of data packets from one or more corresponding crosspoint buffers.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →