Network communications processor architecture with memory load balancing
View Patent ↗Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.
1. In a memory system comprising a plurality of hardware engines, the hardware engines coupled to (i) at least one unidirectional ring bus, and (ii) a plurality of addressable memory arrays, a method of accessing data in the arrays, the method comprising the steps of:
sending, by a source one of the plurality of hardware engines, a task message over the at least one unidirectional ring bus to an adjacent hardware engine coupled to the ring bus, the task message having a corresponding one or more destination hardware engines;
iteratively:
checking, by the adjacent hardware engine, whether the hardware engine is a destination hardware engine for the task message and, if not, passing the task message unchanged to a next adjacent hardware engine coupled to the ring bus, thereby passing the task message from the source hardware engine to each corresponding destination engine on the ring bus;
reading, from the received task message by the corresponding one or more destination hardware engines, a logical address of data in the addressable memory array to be accessed;
computing, by the destination hardware engine, a hash value based on at least a part of the logical address;
selecting one of the plurality of addressable memory arrays based on the hash value; and
accessing the data in the selected addressable memory array using a physical address based on at least part of the logical address not used to compute the hash value.
2. The method of claim 1 , wherein the step of computing the hash value is completed in one clock cycle.
3. The method of claim 1 , wherein the plurality of addressable memory arrays comprises at least a power of two addressable memory arrays.
4. The method of claim 1 , wherein at least a portion of the addressable memory arrays are organized into caches.
5. The method of claim 1 , wherein the hash value is generated to provide random selection of each of the addressable memory arrays.
6. A memory system comprising:
a plurality of hardware engines the hardware engines each coupled to (i) at least one unidirectional ring bus, and (ii) a plurality of addressable memory arrays;
each hardware engine configured to:
send a task message over the at least one unidirectional ring bus to an adjacent hardware engine coupled to the ring bus, the task message having a corresponding one or more destination hardware engines;
check, upon receiving a task message, whether the hardware engine is a destination hardware engine for the task message and, if not, pass the task message unchanged to a next adjacent hardware engine coupled to the ring bus, whereby the task message is passed from the source hardware engine to each corresponding destination engine on the ring bus;
read from the task message, if the hardware engine is a destination engine for the task message, a logical address of data in the addressable memory array to be accessed by the destination hardware engine;
generate a hash value based on at least a part of the logical address;
select one of the plurality of addressable memory arrays based on the hash value; and
access the data in the selected addressable memory array using a physical address based on at least part of the logical address not used to compute the hash value.
7. The memory system of claim 6 , wherein the hardware engine is configured to generate the hash value in one clock cycle.
8. The memory system of claim 6 , wherein the plurality of addressable memory arrays comprises at least a power of two addressable memory arrays.
9. The memory system of claim 6 , wherein the hash value is configured to provide random accesses by the circuit of each of the addressable memory arrays.
10. The memory system of claim 6 , wherein the memory system is implemented in a network processor.
11. The memory system of claim 10 , wherein the network processor is implemented in an integrated circuit chip.
12. The memory system of claim 10 , wherein each of the plurality of addressable memory arrays of the memory system are coupled to one or more processing cores of the network processor by a non-blocking crossbar switch.