IP Library Granted Patent US 8,761,916
Granted Patent B2
US 8,761,916 · App. 13/124,474 · Granted Jun 24, 2014

High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs)

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,761,916
App. No.
13/124,474
Granted
Jun 24, 2014
Kind
B2
Abstract

In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame.

Claims (1383)

1. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform tone detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the tone detection comprises:

(i) determining a power P(F) of a frequency F for the data frame by performing the following operations on the N-sample data frame:

(a) generate V a (n) where V a (n)=M·x nD+a , for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (a) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel;

(

b

)

generate

Re

a

(

n

+

1

)

where

Re

a

(

n

+

1

)

=

Re

a

(

n

)

+

V

a

(

n

)

·

cos

(

2

π

F

F

s

(

n

-

Dn

-

a

)

)

,

for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (b) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel; and

(

c

)

generate

Im

a

(

n

+

1

)

where

Im

a

(

n

+

1

)

=

Im

a

(

n

)

+

V

a

(

n

)

·

sin

(

2

π

F

F

s

(

n

-

Dn

-

a

)

)

,

for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (c) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel, wherein V a (k), Re a (k), and Im a (k) are storage variables, F s is a sampling frequency for the data frame, x i is the ith sample of the data frame, a, k, and n are counting variables, and M is a normalization factor; and

(ii) thresholding the determined power P(F) to determine whether a tone corresponding to the frequency F is present in the audio signal.

2. The DSP of claim 1 , wherein the DSP is adapted to determine the power P(F) in accordance with the equation

P

(

F

)

=

SAT

[

A

+

(

SAT

[

Re

1

(

N

D

)

+

Re

2

(

N

D

)

+

+

Re

D

(

N

D

)

]

)

2

+

(

SAT

[

Im

1

(

N

D

)

+

Im

2

(

N

D

)

+

+

Im

D

(

N

D

)

]

)

2

]

,

where SAT[ ] is a saturation function and A is an additive correction.

3. The DSP of claim 1 , wherein the DSP is adapted to:

(A) initialize Re 1 (0) to

A

·

m

=

0

N

-

1

[

cos

(

2

π

F

F

s

m

)

-

sin

(

2

π

F

F

s

m

)

]

;

(B) initialize Im 1 (0) to

A

·

m

=

0

N

-

1

[

cos

(

2

π

F

F

s

m

)

+

sin

(

2

π

F

F

s

m

)

]

;

 and

(C) initialize Re j (0) and Im j (0) to 0 for j=2, . . . , D, wherein A is an additive correction and m and j are counting variables.

4. The DSP of claim 3 , wherein the DSP is adapted to determine the power P(F) in accordance with the equation

P

(

F

)

=

SAT

[

A

+

(

SAT

[

Re

1

(

N

D

)

+

Re

2

(

N

D

)

+

+

Re

D

(

N

D

)

]

)

2

+

(

SAT

[

Im

1

(

N

D

)

+

Im

2

(

N

D

)

+

+

Im

D

(

N

D

)

]

)

2

]

,

where SAT[ ] is a saturation function and A is an additive correction.

5. The DSP of claim 1 , wherein the DSP is adapted to perform silence detection for the data frame (i) prior to performing tone detection and (ii) using the ALUs of the plurality of D ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal.

6. The DSP of claim 5 , wherein the filtering uses the filter equation below:

z n =A ·(1 +B 0 +B 1 + . . . +B D−3 )+ B 0 ( x n −x n−2 )+ B 1 ( x n−1 −x n−3 )+ B 2 ( x n−2 −x n−4 )+ . . . + B D−3 ( x n−D−3 −x n−D−5 )+ B D−2 ·z n−D+2 +B D−1 ·z n−D+1 ,

where A is an additive correction, B i is the ith multiplicative factor, x i is the ith sample of the data frame, and z n is the filter output.

7. A digital signal processor (DSP) comprising a plurality of 4 arithmetic logic units (ALUs), wherein the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform tone detection for the data frame using the ALUs of the plurality of 4 ALUs in parallel, wherein the tone detection comprises:

(i) determining a power P(F) of a frequency F for the data frame by performing the following operations for n=1, . . . , N/4, wherein the DSP reads a sequential 4-sample group from the N-sample data frame for each value of n:

(a) generate V a (n) where V a (n)=M·x 4n−4+a , for a=1, . . . , 4;

(b) generate Re 1 (n) where

Re

1

(

n

)

=

Re

1

(

n

-

1

)

+

V

1

(

n

)

·

cos

(

2

π

F

F

s

(

N

-

4

n

+

3

)

)

;

(c) generate Im 1 (n) where

Im

1

(

n

)

=

Im

1

(

n

-

1

)

+

V

1

(

n

)

·

sin

(

2

π

F

F

s

(

N

-

4

n

+

3

)

)

;

(d) generate Re 2 (n) where

Re

2

(

n

)

=

Re

2

(

n

-

1

)

+

V

2

(

n

)

·

cos

(

2

π

F

F

s

(

N

-

4

n

+

2

)

)

;

(e) generate Im 2 (n) where

Im

2

(

n

)

=

Im

2

(

n

-

1

)

+

V

2

(

n

)

·

sin

(

2

π

F

F

s

(

N

-

4

n

+

2

)

)

;

(f) generate Re 1 (n) where

Re

1

(

n

)

=

Re

1

(

n

)

+

V

3

(

n

)

·

cos

(

2

π

F

F

s

(

N

-

4

n

+

1

)

)

;

(g) generate Im 1 (n) where

Im

1

(

n

)

=

Im

1

(

n

)

+

V

3

(

n

)

·

sin

(

2

π

F

F

s

(

N

-

4

n

+

1

)

)

;

(h) generate Re 2 (n) where

Re

2

(

n

)

=

Re

2

(

n

)

+

V

4

(

n

)

·

cos

(

2

π

F

F

s

(

N

-

4

n

)

)

;

 and

(i) generate Im 2 (n) where

Im

2

(

n

)

=

Im

2

(

n

)

+

V

4

(

n

)

·

sin

(

2

π

F

F

s

(

N

-

4

n

)

)

,

 wherein V a (n), Re 1 (n), Re 2 (n), Im 1 (n), and Im 2 (n) are storage variables, F s is the sampling frequency for the data frame, x i is the ith sample of the data frame, a is a counting variable, and M is a normalization factor; and

(ii) thresholding the determined power P(F) to determine whether a tone corresponding to the frequency F is present in the audio signal.

8. The DSP of claim 7 , wherein the DSP is adapted to determine the power P(F) in accordance with the equation

P

(

F

)

=

SAT

[

A

+

(

SAT

[

Re

1

(

N

4

)

+

Re

2

(

N

4

)

]

)

2

+

(

SAT

[

Im

1

(

N

4

)

+

Im

2

(

N

4

)

]

)

2

]

,

wherein SAT[ ] is a saturation function and A is an additive correction.

9. The DSP of claim 7 , wherein the DSP is adapted to:

(A) initialize Re 1 (0) to

A

·

m

=

0

N

-

1

[

cos

(

2

π

F

F

s

m

)

-

sin

(

2

π

F

F

s

m

)

]

;

(B) initialize Im 1 (0) to

A

·

m

=

0

N

-

1

[

cos

(

2

π

F

F

s

m

)

+

sin

(

2

π

F

F

s

m

)

]

;

 and

(C) initialize Re 2 (0) and Im 2 (0) to 0, wherein A is an additive correction and m is a counting variable.

10. The DSP of claim 7 , wherein the DSP is adapted to:

perform operations (a) in one clock cycle for any one value of n by using all the ALUs of the plurality of 4 ALUs in parallel;

perform operations (b)-(e) in one clock cycle for any one value of n by using all the ALUs of the plurality of 4 ALUs in parallel; and

perform operations (f)-(i) in one clock cycle for any one value of n by using all the ALUs of the plurality of 4 ALUs in parallel.

11. The DSP of claim 7 , wherein the DSP is adapted to perform silence detection for the data frame (i) prior to performing tone detection and (ii) using all the ALUs of the plurality of 4 ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal.

12. The DSP of claim 11 , wherein the filtering uses the filter equation below:

z n =A ·(1+ B 0 +B 1 + . . . +B D−3 )+ B 0 ( x n −x n−2 )+ B 1 ( x n−1 −x n−3 )+ B 2 ( x n−2 −x n−4 )+ . . . + B D−3 ( x n−D−3 −x n−D−5 )+ B D−2 ·z n−D+2 +B D−1 ·z n−D+1 ,

where A is an additive correction, B i is the ith multiplicative factor, x i is the ith sample of the data frame, and z n is the filter output.

13. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform tone detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the tone detection comprises:

(i) determining a power P(F) of a frequency F for the data frame by performing the following operations on the N-sample data frame:

(a) initialize Re(0) and Im(0) to 0;

(b) for n=1, . . . , [N/2D]:

(1) generate Re 1 (n) where

Re

1

(

n

)

=

A

·

s

=

0

D

[

cos

(

s

α

)

-

sin

(

s

α

)

]

+

s

=

1

D

[

cos

(

s

α

)

·

M

·

x

2

D

n

-

D

-

s

]

+

cos

(

D

α

)

·

Re

(

n

-

1

)

-

sin

(

D

α

)

·

Im

(

n

-

1

)

+

M

·

x

2

Dn

-

D

;

(2) generate Im 1 (n) where

Im

1

(

n

)

=

A

·

s

=

0

D

[

cos

(

s

α

)

+

sin

(

s

α

)

]

+

s

=

1

D

[

sin

(

s

α

)

·

M

·

x

2

Dn

-

D

-

s

]

+

sin

(

D

α

)

·

Re

(

n

-

1

)

+

cos

(

D

α

)

·

Im

(

n

-

1

)

;

(3) generate Re(n) where Re(n)=SAT[Re 1 (n)];

(4) generate Im(n) where Im(n)=SAT[Im 1 (n)];

(5) generate Re 2 (n) where

Re

2

(

n

)

=

A

·

s

=

0

D

[

cos

(

s

α

)

-

sin

(

s

α

)

]

+

s

=

1

D

[

cos

(

s

α

)

·

M

·

x

2

Dn

-

s

]

+

cos

(

D

α

)

·

Re

(

n

)

-

sin

(

D

α

)

·

Im

(

n

)

+

M

·

x

2

Dn

;

 and

(6) generate Im 2 (n) where

Im

2

(

n

)

=

A

·

s

=

0

D

[

cos

(

s

α

)

+

sin

(

s

α

)

]

+

s

=

1

D

[

sin

(

s

α

)

·

M

·

x

2

Dn

-

s

]

+

sin

(

D

α

)

·

Re

(

n

)

+

cos

(

D

α

)

·

Im

(

n

)

;

(7) generate Re(n) where Re(n)=SAT[Re 2 (n)];

(8) generate Im(n) where Im(n)=SAT[Im 2 (n)]; and

(c) generate P(F) where P(F)=Re(N/2D) 2 +Im(N/2D) 2 , wherein Re(n), Re 1 (n), Re 2 (n), Im(n), Im 1 (n), and Im 2 (n) are storage variables, s is a counting variable, A is an additive correction, M is a normalization factor, SAT[ ] is a saturation function, and α is 2πF/F s , where F s is a sampling frequency for the data frame; and

(ii) thresholding the determined power P(F) to determine whether a tone corresponding to the frequency F is present in the audio signal.

14. The DSP of claim 13 , wherein the DSP is adapted to perform silence detection for the data frame (i) prior to performing tone detection and (ii) using the ALUs of the plurality of D ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal.

15. The DSP of claim 14 , wherein the filtering uses the filter equation below:

z n =A ·(1+ B 0 +B 1 + . . . +B D−3 )+ B 0 ( x n −x n−2 )+ B 1 ( x n−1 −x n−3 )+ B 2 ( x n−2 −x n−4 )+ . . . + B D−3 ( x n−D−3 −x n−D−5 )+ B D−2 ·z n−D+2 +B D−1 ·z n−D+1 ,

where A is an additive correction, B i is the ith multiplicative factor, x i is the ith sample of the data frame, and z n is the filter output.

16. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein:

the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform silence detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal; and

the filtering uses the filter equation below:

z n =A ·(1 +B 0 +B 1 + . . . +B D−3 )+ B 0 ( x n −x n−2 )+ B 1 ( x n−1 −x n−3 )+ B 2 ( x n−2 −x n−4 )+ . . . + B D−3 ( x n−D−3 −x n−D−5 )+ B D−2 ·z n−D+2 +B D−1 ·z n−D+1 ,

where A is an additive correction, B i is the ith multiplicative factor, x i is the ith sample of the data frame, and z n is the filter output.

17. The DSP of claim 16 , wherein:

(A) B 0 =B 0 ;

(B) B 1 =A·B 0 ; and

(C) for i=2 to D−3

B i +A 2 ·B i−2 , where A i and B i are multiplicative factors.

18. The DSP of claim 17 , wherein B 0 is 0.825, A 1 is −0.16, and A 2 is −0.6499.

19. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein:

the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform silence detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal; and

the DSP comprises at least four ALUs and silence detection comprises performing the filtering operations below for n=2, 4, 6, . . . , N:

(1) q n =A;

(2) q n−1 =A;

(3) q n =q n −B 0 ·x n−2 ;

(4) q n−1 =q n−1 −B 0 ·x n−3 ;

(5) read x n−1 and x n ;

(6) q n =q n +B 0 ·x n ;

(7) q n−1 =q n−1 +B 0 ·x n−1 ;

(8) z n =q n ;

(9) z n−1 =q n−1 ;

(10) z n =z n +A 1 ·z n−1 ;

(11) z n =z n +A 1·2 ·z n-3 ;

(12) z n−1 =z n−1 +A 2 ·z n−3 ;

(13) z n =z n +A 1·1+2 ·z n−2 ;

(14) z n−1 =z n−1 +A 1 ·z n−2 ; and

(15) write z n−1 and z n , where z k is an output of the silence detection, q k is storage variable, A is an additive correction, k and n are counting variables, B 0 , A 1 , and A 2 are multiplicative factors, A 1·2 represents A 1 ·A 2 , and A 1·1+2 represents A·A 1 +A 2 .

20. The DSP of claim 19 , wherein the DSP is adapted to perform:

(A) operations (1)s, (2)s, (8)s−2, (9)s−2, (11)s−4, (12)s−4 in parallel and in one clock cycle;

(B) operations (3)s, (4)s, (5)s, (13)s−4, (14)s−4 in parallel and in one clock cycle; and

(C) operations (6)s−2, (7)s−2, (10)s−2, (15)s−4 in parallel and in one clock cycle, where the subscript indices s, s−2, and s−4 correspond to values of n for which the corresponding operation is performed.

21. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein:

the DSP is adapted to:

receive an N-sample data frame comprising digital samples corresponding to an audio signal; and

perform silence detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the silence detection comprises filtering a given frequency range of the signal;

the filtering uses the filter equation below:

z n =A ·(1 +B 0 +B 1 + . . . +B D−3 )+ B 0 ( x n −x n−2 )+ B 1 ( x n−1 −x n−3 )+ B 2 ( x n−2 −x n−4 )+ . . . + B D−3 ( x n−D−3 −x n−D−5 )+ B D−2 ·z n−D+2 +B D−1 ·z n−D+1 ,

where A is an additive correction, B i is the ith multiplicative factor, x i is the ith sample of the data frame, and z n is the filter output; and

the DSP performs tone detection for the data frame if and only if the DSP determined, in performing the silence detection for the data frame, that the data frame does not represent silence.

22. The DSP of claim 21 , wherein the DSP performs tone detection for the data frame (i) after performing the silence detection and (ii) using the ALUs of the plurality of D ALUs in parallel, wherein the tone detection comprises (i) determining a power P(F) of a frequency F for the data frame and (ii) thresholding the determined power P(F) to determine whether a tone corresponding to the frequency F is present in the audio signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2011
From: LETUNOVSKIY, ALEKSEY ALEXANDROVICH; LYALIN, ILYA VIKTOROVICH; MARKOVIC, ALEXANDER; MAZURENKO, IVAN LEONIDOVICH; NIKITIN, ANDREY ANDREY
To: LSI CORPORATION
Reel/Frame 026135/0744 →