Controlling timeslot delay in a digital communication system

1. A buffer circuit for use in a digital communication system, the buffer circuit comprising:

a memory configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system; and

a controller coupled to the memory, the controller being operative: (i) to store data from the first data stream into corresponding timeslots in the memory in a first order; (ii) to individually adjust delays of the timeslots in the memory as a function of respective delay control parameters; and (iii) to generate a second data stream by reading the timeslots stored in the memory in a second order;

wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots; and

wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.

2. The circuit of claim 1 , wherein the controller is further operative to receive the first data stream and delay control parameters corresponding to the timeslots.

3. The circuit of claim 1 , wherein the first order in which data from the first data stream is stored in the memory is the function of the delay control parameters corresponding to the timeslots, such that the delay adjustments to the respective timeslots are incorporated into relative positions of the timeslots in the memory, and wherein the second order is sequential.

4. The circuit of claim 1 , wherein the first order in which data from the first data stream is stored in the memory is sequential, and the second order in which the second data stream is read from the memory is the function of the delay control parameters corresponding to the timeslots.

5. The circuit of claim 1 , wherein the first data stream is an input data stream, and the second data stream is an output data stream.

6. The circuit of claim 1 , wherein the controller comprises:

a counter operative to sequentially generate a count signal indicative of a number of each of the timeslots in a given one of the data frames in the memory;

a write address generator operative to generate a write address signal for selectively accessing each of the timeslots in each of the data frames in the memory;

a register for storing the delay control parameters; and

an address modification circuit operative to scale the write address signal and generate a modified write address signal as a function of the delay control parameters of the respective timeslots indicated by the count signal.

7. The circuit of claim 1 , wherein the controller comprises:

a register for storing the delay control parameters; and

a read address generator operative to generate a read address for selectively accessing each of the timeslots in the memory, the read address being a function of the delay control parameters.

8. The circuit of claim 1 , wherein the memory comprises a first-in-first-out register configurable for writing data in a random access manner and for reading data out sequentially.

9. The circuit of claim 1 , wherein the memory comprises a first-in-first-out register configurable for writing data sequentially and for reading data out in a random access manner.

10. The circuit of claim 1 , wherein the controller comprises:

a write address generator operative to generate a write address for selectively writing each of the timeslots in each of the data frames in the memory;

a read address generator operative to generate a read address for selectively reading each of the timeslots in each of the data frames in the memory; and

a comparator operative to receive the write address and the read address, and to generate an output signal that is a function of a difference between the write address and the read address.

11. The circuit of claim 1 , wherein the controller comprises:

a read address generator operative to generate a read address signal for selectively accessing each of the timeslots in each of the data frames in the memory;

a register for storing the delay control parameters; and

an address modification circuit operative to scale the read address signal and generate a modified read address signal as a function of the delay control parameters of the respective timeslots.

12. The circuit of claim 1 , wherein the timeslots comprise digital signal 0 (DS0) timeslots on a digital signal 1 (DS1) link in the digital communication system.

13. The circuit of claim 1 , wherein the controller comprises frame selection circuitry operative: (i) to configure the timeslots in accordance with a first frame format in a first mode of operation; and (ii) to configure the timeslots in accordance with a second frame format in a second mode of operation.

14. The circuit of claim 13 , wherein the first frame format is a T-carrier 1 (T1) format, and the second frame format is an E-carrier 1 (E1) format.

15. The buffer circuit of claim 1 , wherein the first order and the second order are orderings of timeslots within a given data frame such that successive data frames within a given data stream have the same ordering of timeslots.

16. An integrated circuit including at least one buffer circuit for use in a digital communication system, the at least one buffer circuit comprising:

a memory configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system; and

a controller coupled to the memory, the controller being operative: (i) to store data from the first data stream into corresponding timeslots in the memory in a first order; (ii) to individually adjust delays of the timeslots in the memory as a function of respective delay control parameters; and (iii) to generate a second data stream by reading the timeslots stored in the memory in a second order;

wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots; and

wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.

17. The integrated circuit of claim 16 , wherein the first order in which data from the first data stream is stored in the memory is the function of the delay control parameters corresponding to the timeslots, such that the delay adjustments to the respective timeslots are incorporated into relative positions of the timeslots in the memory, and wherein the second order is sequential.

18. The integrated circuit of claim 16 , wherein the controller comprises:

a counter operative to sequentially generate a count signal indicative of a number of each of the timeslots in a given one of the data frames in the memory;

a write address generator operative to generate a write address signal for selectively accessing each of the timeslots in each of the data frames in the memory;

a register for storing the delay control parameters; and

an address modification circuit operative to scale the write address signal and generate a modified write address signal as a function of the delay control parameters of the respective timeslots indicated by the count signal.

19. The integrated circuit of claim 16 , wherein the controller comprises:

a register for storing the delay control parameters; and

a read address generator operative to generate a read address for selectively accessing each of the timeslots in the memory, the read address being a function of the delay control parameters.

20. A non-transitory computer-readable storage medium for individually controlling a delay of each of a plurality of timeslots on a given link in a digital communication system, the non-transitory computer-readable storage medium containing one or more programs which when executed implement the steps of:

storing timeslots of each of a plurality of data frames of a first data stream into corresponding timeslots in a memory in a first order;

individually adjusting delays of the timeslots in the memory as a function of respective delay control parameters; and

generating a second data stream by reading the timeslots stored in the memory in a second order;

wherein the timeslots in the memory correspond to respective channels in the digital communication system;

wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots; and

wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.