IP Library Granted Patent US 7,580,426
Granted Patent B2
US 7,580,426 · App. 11/536,191 · Granted Aug 25, 2009

Interface with multilevel packet preemption based on balancing of start and end indicators

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Quick Facts
Patent No.
US 7,580,426
App. No.
11/536,191
Granted
Aug 25, 2009
Kind
B2
Abstract

Preemption techniques for use in conjunction with an interface between a physical layer device and a link layer device are disclosed. Segments associated with or comprising packets, cells or other protocol data units (PDUs) are communicated between the physical layer device and the link layer device via an interface bus. At least first and second consecutive start indicators having respective first and second data segments associated therewith are received by one of the devices from the other, and the second data segment is permitted to preempt the first data segment without signaling an interface protocol violation, subject to subsequent confirmation that the preemption is appropriate. If a number of consecutive end indicators is subsequently received that balances the number of consecutive start indicators, the preemption is confirmed as appropriate, and otherwise an interface protocol violation is signaled.

Claims (32)

1. A method comprising the step of:

processing data segments communicated between a first device and a second device via an interface bus:

the processing step further comprising the steps of:

receiving in one of the first and second devices from the other of the first and second devices at least first and second consecutive start indicators having respective first and second data segments associated therewith;

allowing the second data segment to preempt the first data segment without signaling an interface protocol violation, subject to subsequent confirmation that the preemption is appropriate;

if a number of consecutive end indicators is subsequently received that balances the at least first and second consecutive start indicators, confirming that the preemption is appropriate, and otherwise signaling an interface protocol violation.

2. The method of claim 1 wherein the first and second data segments comprise respective first and second packets.

3. The method of claim 2 wherein the start indicators comprise start of packet indicators and the end indicators comprise end of packet indicators.

4. The method of claim 2 wherein an arbitrary number n of consecutive start indicators are received for n respective packets, and preemption of each of n−1 packets by packet n is confirmed by subsequent receipt of n consecutive end indicators.

5. The method of claim 1 wherein the interface is configured in accordance with a POS-2 interface protocol.

6. The method of claim 1 wherein the interface is configured in accordance with a SPI-3 interface protocol.

7. The method of claim 1 wherein the data segments are directed to a common MPHY address.

8. The method of claim 1 wherein said at least first and second consecutive start indicators comprise multiple consecutive assertions of an xSOP signal for a same MPHY without intervening assertions of an xEOP signal.

9. The method of claim 8 wherein multiple consecutive assertions of the xSOP signal for the same MPHY without intervening assertions of the xEOP signal are recognized as being indicative of appropriate preemptions if and only if followed by an equivalent number of consecutive assertions of the xEOP signal.

10. An apparatus comprising:

a first device configured for communication with a second device via an interface bus;

the first device comprising interface circuitry configured to receive from the second device at least first and second consecutive start indicators having respective first and second data segments associated therewith, and to allow the second data segment to preempt the first data segment without signaling an interface protocol violation, subject to subsequent confirmation that the preemption is appropriate;

wherein if a number of consecutive end indicators is subsequently received that balances the at least first and second consecutive start indicators, the preemption is confirmed as appropriate, and otherwise an interface protocol violation is signaled.

11. The apparatus of claim 10 wherein the first device comprises a physical layer device and the second device comprises a link layer device.

12. The apparatus of claim 11 wherein the physical layer device is implemented as an integrated circuit.

13. The apparatus of claim 11 wherein the physical layer device comprises a digital subscriber line transceiver.

14. The apparatus of claim 10 wherein the first device comprises a link layer device and the second device comprises a physical layer device.

15. The apparatus of claim 14 wherein the link layer device is implemented as an integrated circuit.

16. The apparatus of claim 14 wherein the link layer device comprises a network processor.

17. A communication system comprising:

a link layer device; and

a physical layer device;

the link layer device and the physical layer device being coupled together via an interface bus;

at least one of the link layer device and the physical layer device being configured to receive from the other at least first and second consecutive start indicators having respective first and second data segments associated therewith, and to allow the second data segment to preempt the first data segment without signaling an interface protocol violation, subject to subsequent confirmation that the preemption is appropriate, wherein if a number of consecutive end indicators is subsequently received that balances the at least first and second consecutive start indicators, the preemption is confirmed as being appropriate, and otherwise an interface protocol violation is signaled.

18. The system of claim 17 wherein an arbitrary number n of consecutive start indicators are received for n respective packets, and preemption of each of n−1 packets by packet n is confirmed by subsequent receipt of n consecutive end indicators.

19. The system of claim 17 wherein said at least first and second consecutive start indicators comprise multiple consecutive assertions of an xSOP signal for a same MPHY without intervening assertions of an xEOP signal.

20. The system of claim 19 wherein multiple consecutive assertions of the xSOP signal for the same MPHY without intervening assertions of the xEOP signal are recognized as being indicative of appropriate preemptions if and only if followed by an equivalent number of consecutive assertions of the xEOP signal.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
CERTIFICATE OF CONVERSION Recorded Oct 19, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034014/0846 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →