Processor with programmable configuration of logical-to-physical address translation on a per-client basis
A network processor or other type of processor includes translation configuration circuitry which allows programmable configuration of logical-to-physical address translation on a per-client basis for multiple clients of the processor. In one aspect of the invention, the processor stores translation configuration information for a client. A read or write request from the client includes a logical address. The logical address is processed utilizing the stored translation configuration information for the client to generate a physical address. The physical address is utilized to access an internal or external memory.
1. A processor comprising:
a plurality of clients;
translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client; and
memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address;
wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
2. The processor of claim 1 wherein the plurality of clients comprises at least one of a segmentation engine, a classification engine, a protocol data unit buffer controller, a general-purpose processing core, a queuing engine, a traffic manager and a link list controller.
3. The processor of claim 1 wherein the given one of the translation configuration registers stores information specifying a particular number of banks of a multiple-bank memory that are allocated to the given client.
4. The processor of claim 3 wherein the given one of the translation configuration registers stores information specifying which of the number of banks allocated to the given client are to be used for an associated transfer.
5. The processor of claim 1 wherein the given one of the translation configuration registers stores information specifying one or more bits of a logical address that are to be used to determine a bank portion of the physical address.
6. The processor of claim 1 wherein the address translation circuitry comprises logical-to-physical address translation logic.
7. The processor of claim 1 wherein the memory comprises an external memory coupled to the memory controller via an external memory interface of the processor.
8. The processor of claim 1 wherein the memory comprises an internal memory of the processor.
9. The processor of claim 1 wherein the client request further specifies a length of a corresponding data transfer.
10. The processor of claim 9 wherein the address translation circuitry determines a number of native size transfers corresponding to the transfer length specified in the client request.
11. The processor of claim 1 wherein the address translation circuitry processes the client request to determine page control information suitable for delivery to the memory controller.
12. The processor of claim 1 wherein the configuration information stored in the translation configuration circuitry is updatable under control of a processing unit.
13. The processor of claim 1 wherein the processor comprises a network processor.
14. The processor of claim 1 wherein the processor is configured as an integrated circuit.
15. The processor of claim 1 , wherein the first and second portions of the given one of the translation configuration registers for the given client are different than first and second portions of at least another one of the plurality of configuration registers associated with another one of the plurality of clients.
16. The processor of claim 1 , wherein the first portion of translation logic specifies a width of the memory interface.
17. The processor of claim 16 , wherein the second portion of translation logic specifies a bank portion of the physical address.
18. The processor of claim 17 , wherein the given one of the translation configuration registers further comprises third and fourth portions specifying respective third and fourth sets of bit locations of the logical address that are to be used to determine respective third and fourth portions of translation logic, the third portion of translation logic specifying a particular number of banks of a multiple-bank memory allocated to the given client and the fourth portion of translation logic specifying which of the number of banks allocated to the given client are to be used for an associated transfer.
19. A processing system comprising:
a processor; and
an external memory operatively coupled to the processor;
the processor further comprising:
a plurality of clients;
translation configuration circuitry comprising a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
address translation circuitry coupled to the translation configuration circuitry, the address translation circuitry being configured to utilize the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client; and
memory controller circuitry coupled to the address translation circuitry, the memory controller circuitry being configured to access a memory utilizing the physical address;
wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
20. A method for use in processing packets in a processor, the processor comprising a plurality of clients, the method comprising the steps of:
storing translation configuration information for the plurality of clients of the processor in a plurality of translation configuration registers, a given one of the plurality of translation configuration registers storing translation configuration information for at least a given one of the plurality of clients;
utilizing the translation configuration information for the given client to generate a physical address from a logical address specified in a request from the given client; and
accessing a memory utilizing the received physical address;
wherein the given one of the translation configuration registers comprises at least a first portion and a second portion, the first and second portions specifying respective first and second sets of bit locations of the logical address that are to be used to determine respective first and second portions of translation logic for the given client.
21. The method of claim 20 wherein the given one of the translation configuration registers stores information specifying one or more bits of the logical address that are to be used to determine the bank portion of a physical address.