Method and apparatus for establishing a bound on the effect of task interference in a cache memory
View Patent ↗A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is the maximum number of “live” frames of a given task that are coexistent during the execution of an application. A “live cache frame” contains a block that is accessed in the future without an intervening eviction. The eviction of blocks from a live frame by an interrupt causes a future miss that would not otherwise occur and evictions from live frames are the only evictions that cause misses that would not otherwise occur. The invention provides a more accurate estimate of the maximum addition time of a task that results from servicing an interrupt during its execution. Additional accuracy is obtained by exploiting knowledge of the character of an intervening task to achieve a tighter bound, when possible.
1. A method for establishing a bound on the execution time of an application due to task interference in an instruction cache shared by a plurality of tasks, said method comprising the steps of:
determining a number of live frames of said application that are coexistent during execution of said application; and
establishing said bound based on said number of live frames, wherein said bound is suitable for use in allocating processing resources, and wherein said step of establishing said bound further comprises the step of comparing sets that contain live frames of said application with sets accessed by an interrupting task to determine a maximum number of live-frames that may be affected by an interrupting task.
2. The method of claim 1 , wherein said number of live frames is a number of cache frames that contain a block that is accessed by said application in the future without an intervening eviction.
3. The method of claim 1 , wherein said number of live frames is determined by a post-execution analysis of cache access patterns of said application.
4. The method of claim 1 , wherein said number of live frames is determined by a run-time analysis of cache access patterns of a simulation of said application.
5. The method of claim 1 , wherein said step of establishing said bound further comprises the steps of determining an effect of an interrupt at each possible interrupt point and establishing said bound based on a maximum of said effect of an interrupt at each possible interrupt point.
6. A system for establishing a bound on the execution time of an application due to task interference in an instruction cache shared by a plurality of tasks, said system comprising:
a memory that stoles computer-readable code; and
a processor operatively coupled to said memory, said processor configured to implement said computer-readable code, said computer-readable code configured to:
determine a number of live frames of said application that are coexistent during execution of said application; and
establish said bound based on said number of live frames, wherein said bound is suitable for use in allocating processing resources, and wherein said processor is further configured to compare sets that contain live frames of said application with sets accessed by an interrupting task to determine a maximum number of live-frames that may be affected by an interrupting task.
7. The system of claim 6 , wherein said number of live frames is a number of cache frames that contain a block that is accessed by said application in the future without an intervening eviction.
8. The system of claim 6 , wherein said number of live frames is determined by a post-execution analysis of cache access patterns of said application.
9. The system of claim 6 , wherein said number of live frames is determined by a run-time analysis of cache access patterns of a simulation of said application.
10. The system of claim 6 , wherein said processor is farther configured to determine an effect of an interrupt at each possible interrupt point and establish said bound based on a maximum of said effect of an interrupt at each possible interrupt point.
11. An article of manufacture for establishing a bound on the execution time of an application due to task interference in an instruction cache shared by a plurality of tasks, comprising:
a computer recordable medium having computer instructions embodied thereon, said instructions when executed by a computer to perform the steps comprising:
a step to determine a number of live frames of said application that are coexistent during execution of said application;
a step to establish said bound based on said number of live frames, wherein said bound is suitable for use in allocating processing resources, and a step to compare sets that contain live frames of said application with sets accessed by an interrupting task to determine a maximum number of live frames that may be affected by an interrupting task.
12. The article of manufacture of claim 11 , wherein the instructions further performs a step to determine an effect of an interrupt at each possible interrupt and establish said bound based on a maximum of said effect of an interrupt at each possible interrupt point.
13. A system having a processor for establishing a bound on an effect of task interference on an application in an instruction cache shared by a plurality of tasks, said system comprising:
means for determining a number of live frames of said application that are coexistent during execution of said application; and
means for establishing said bound based on said number of live frames, wherein said bound is suitable for use in allocating processing resources, and further comprising means for comparing sets that contain live frames of said application with sets accessed by an interrupting task to determine a maximum number of live frames that may be affected by an interrupting task.
14. The system of claim 13 , wherein said number of live frames is determined by a post-execution analysis of cache access patterns of said application.
15. The system of claim 13 , wherein said number of live frames is determined by a run-time analysis of cache access patterns of a simulation of said application.
16. The system of claim 13 , further comprising means for determining an effect of an interrupt at each possible interrupt point and establish said bound based on a maximum of said effect of an interrupt at each possible interrupt point.