Method and apparatus for N+1 packet level mesh protection
View Patent ↗Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m 0 through m N-1 , to generate a codeword that includes the message symbols, m 0 through m N-1 , and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m 0 through m N-1 , through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m 0 through m N-1 , and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m 0 through m N-1 , and the one or more check symbols through the linear feedback shift register.
1. An error correction encoder for encoding message symbols, m 0 through m N-1 , to generate an error correction codeword that includes said message symbols, m 0 through m N-1 , and one or more check symbols, comprising:
a linear feedback shift register having one or more flip-flops to generate said check symbols for said error correction codeword after shifting said message symbols, m 0 through m N-1 , through said linear feedback shift register, wherein each error correction codeword includes said message symbols, m 0 through m N-1 , and said corresponding generated check symbols.
2. An error correction encoder for encoding message symbols, m 0 through m N-1 , to generate an error correction codeword that includes said message symbols, m 0 through m N-1 , and one or more check symbols, comprising:
a linear feedback shift register having one or more flip-flops to generate said check symbols for said error correction codeword after shifting said message symbols, m 0 through m N-1 , through said linear feedback shift register, wherein a payload containing said message symbols, m 0 through m N-1 , comprises a symbol-wise exclusive or (XOR) of said message symbols, m 0 through m N-1 .
3. An error correction decoder for decoding an error correction codeword that includes message symbols, m 0 through m N-1 , and one or more corresponding check symbols, comprising:
a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting said message symbols, m 0 through m N-1 , and said one or more check symbols of said error correction codeword through said linear feedback shift register, wherein each error correction codeword includes said message symbols, m 0 through m N-1 , and said one or more corresponding check symbols.
4. An error correction decoder for decoding an error correction codeword that includes message symbols, m 0 through m N-1 , and one or more check symbols, comprising:
a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting said message symbols, m 0 through m N-1 , and said one or more check symbols of said error correction codeword through said linear feedback shift register, wherein said error symbol is said remainder for T equal to one check symbol, where T is a number of protection packets.