Synchronous transport signal mapper with payload extraction and insertion functionality
View Patent ↗In a communication system comprising a mapper or other type of physical layer device coupled to a link layer device, the physical layer device comprises payload extraction circuitry and payload insertion circuitry. The payload extraction circuitry is configured to extract a payload from an ingress synchronous transport signal received over an ingress link, and the payload insertion circuitry is configured to insert a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link. The payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device over an output serial data line of a serial interface, and the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device over an input serial data line of the serial interface.
1. A physical layer device for communication with a link layer device in a network-based communication system, the physical layer device comprising:
payload extraction circuitry which extracts a payload from an ingress synchronous transport signal received over an ingress link; and
payload insertion circuitry which inserts a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link;
wherein the payload extracted from the ingress synchronous transport signal is converted from parallel to serial form in the payload extraction circuitry and transmitted by the physical layer device to the link layer device in serial form in over an output serial data line of a serial interface; and
wherein the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device in serial form over an input serial data line of the serial interface and converted from serial to parallel form in the payload insertion circuitry.
2. The physical layer device of claim 1 wherein the physical layer device comprises a mapper.
3. The physical layer device of claim 1 further comprising:
a demultiplexer having an input coupled to the ingress link, the demultiplexer being configured to separate the ingress synchronous transport signal from a corresponding higher-rate optical signal received over the ingress link;
a multiplexer having an output coupled to the egress link, the multiplexer being configured to combine the egress synchronous transport signal into a corresponding higher-rate optical signal transmitted over the egress link; and
a switching element coupled between an output of the payload insertion circuitry and an input of the multiplexer and between an output of the demultiplexer and an input of the payload extraction circuitry;
the switching element controlling delivery of the ingress synchronous transport signal from the demultiplexer to the payload extraction circuitry and delivery of the egress synchronous transport signal from the payload insertion circuitry to the multiplexer.
4. The physical layer device of claim 3 further comprising mapping circuitry coupled to the switching element and configured to control switching operations of the switching element.
5. The physical layer device of claim 1 wherein the ingress and egress synchronous transport signals each comprise an STS-3c signal or an STM-1 signal.
6. The physical layer device of claim 3 wherein the higher-rate optical signals each comprise an OC-12 signal or an STM-4 signal.
7. The physical layer device of claim 1 wherein the serial interface over which the payload extracted from the ingress synchronous transport signal is transmitted by the physical layer device to the link layer device and over which the payload inserted in the egress synchronous transport signal is received by the physical layer device from the link layer device comprises a network serial multiplexed interface.
8. The physical layer device of claim 1 wherein the serial interface further comprises input and output gapped clock signal lines.
9. The physical layer device of claim 8 wherein the serial interface comprises input and output byte mark signal lines.
10. The physical layer device of claim 9 wherein the serial interface comprises separate output extraction and insertion synchronization signal lines for carrying respective extraction and insertion synchronization signals for use by the link layer device in processing information associated with the respective extracted and inserted payloads.
11. The physical layer device of claim 10 wherein said physical layer device is configured to provide a programmable delay between a given pulse of the insertion synchronization signal and a designated bit of the inserted payload.
12. The physical layer device of claim 11 wherein the designated bit comprises a most significant bit of a given byte of the inserted payload.
13. An integrated circuit comprising the physical layer device of claim 1 .
14. A link layer device for communication with a physical layer device in a network-based communication system, the link layer device comprising:
interface circuitry which provides a link layer device portion of a serial interface between the link layer device and the physical layer device;
the interface circuitry receiving over a first serial data line of the serial interface a payload extracted by the physical layer device from an ingress synchronous transport signal received by the physical layer device over an ingress link; and
the interface circuitry transmitting over a second serial data line of the serial interface a payload to be inserted by the physical layer device into an egress synchronous transport signal for transmission by the physical layer device over an egress link;
wherein the payload extracted from the ingress synchronous transport signal is converted from parallel to serial form in payload extraction circuitry of the physical layer device; and
wherein the payload inserted into the egress synchronous transport signal is converted from serial to parallel form in payload insertion circuitry of the physical layer device.
15. The link layer device of claim 14 wherein said device comprises at least one of a link layer processor and a field programmable gate array.
16. An integrated circuit comprising the link layer device of claim 14 .
17. A node of a network-based communication system, said node comprising:
a physical layer device; and
a link layer device coupled to the physical layer device;
wherein the physical layer device comprises:
payload extraction circuitry which extracts a payload from an ingress synchronous transport signal received over an ingress link; and
payload insertion circuitry which inserts a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link;
wherein the payload extracted from the ingress synchronous transport signal is converted from parallel to serial form in the payload extraction circuitry and transmitted by the physical layer device to the link layer device in serial form over an output serial data line of a serial interface; and
wherein the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device in serial form over an input serial data line of the serial interface and converted from serial to parallel form circuitry.
18. The node of claim 17 wherein said physical layer and link layer devices comprise respective integrated circuits.
19. A network-based communication system, said system comprising:
a plurality of interconnected nodes;
wherein at least a given one of said nodes comprises:
a physical layer device; and
a link layer device coupled to the physical layer device;
wherein the physical layer device comprises:
payload extraction circuitry which extracts a payload from an ingress synchronous transport signal received over an ingress link; and
payload insertion circuitry which inserts a payload received from the link layer device into an egress synchronous transport signal for transmission over an egress link;
wherein the payload extracted from the ingress synchronous transport signal is converted from parallel to serial form in the payload extraction circuitry and transmitted by the physical layer device to the link layer device in serial form over an output serial data line of a serial interface; and
wherein the payload inserted into the egress synchronous transport signal is received by the physical layer device from the link layer device in serial form over an input serial data line of the serial interface and converted from serial to parallel foim in the payload insertion circuitry.
20. The system of claim 19 wherein the serial interface further comprises input and output gapped clock signal lines, input and output byte mark signal lines, and separate output extraction and insertion synchronization signal lines for carrying respective extraction and insertion synchronization signals for use by the link layer device in processing information associated with the respective extracted and inserted payloads.