Granted Patent B2

US 7,912,069 · App. 11/299,645 · Granted Mar 22, 2011

Abstract

Claims (47)

1. A routing switch processor, comprising:

a memory;

an input interface configured to receive a protocol data unit and classification information determined from said protocol data unit, said classification information being used to determine a port and associated routing switch processor selected for said protocol data unit;

a protocol data unit receiver subsystem configured to (i) receive from said input interface at least a portion of payload data of said protocol data unit, and routing information associated with said protocol data unit, and (ii) store in said memory said at least a portion of payload data in at least two non-contiguous memory blocks being interleaved with payload data from another different protocol data unit; and

a virtual segmentation subsystem, associated with said protocol data unit receiver subsystem, configured to perform virtual segmentation on said protocol data unit by segmenting said at least a portion of payload data when retrieved without reassembling an entirety of said protocol data unit.

2. The routing switch processor as recited in claim 1 wherein said protocol data unit receiver subsystem further includes:

an assembler subsystem configured to receive said at least a portion of payload data and assemble said protocol data unit; and

a transmit queue subsystem configured to maintain a linked list associated with said protocol data unit, perform a function on said protocol data unit and maintain at least one queue structure for transmission.

3. The routing switch processor as recited in claim 2 wherein said assembler subsystem is further configured to store said at least a portion of payload data in said at least two non-contiguous blocks and said transmit queue subsystem is further configured to maintain a linked list of said at least two non-contiguous blocks.

4. The routing switch processor as recited in claim 1 wherein said virtual segmentation subsystem further includes a stream editor subsystem configured to perform said virtual segmentation.

5. The routing switch processor as recited in claim 4 wherein said stream editor subsystem is further configured to convert between a first protocol and a second protocol.

6. The routing switch processor as recited in claim 4 wherein said stream editor subsystem is further configured to generate a validity check selected from the group consisting of:

a cyclic redundancy check (CRC),

a CRC for asynchronous transfer mode (ATM) adaptive layer 5 (AAL5) over ATM, and

a CRC-10 for operation, administration, maintenance (OAM) cells.

7. The routing switch processor as recited in claim 1 wherein said protocol data unit receiver subsystem and said virtual segmentation subsystem are further configured to process a plurality of interleaved portions of different protocol data units.

8. A method of operating a routing switch processor, comprising:

receiving a protocol data unit and classification information determined from said protocol data unit, said classification information being used to determine a port and associated routing switch processor selected for said protocol data unit;

storing at least a portion of payload data from said protocol data unit in at least two non-contiguous memory blocks being interleaved with payload data from another different protocol data unit; and

performing virtual segmentation on said protocol data unit by segmenting said at least a portion of payload data when retrieved without reassembling an entirety of said protocol data unit.

9. The method as recited in claim 8 further comprising:

assembling said protocol data unit with an assembler subsystem; and

maintaining a linked list associated with said protocol data unit, performing a function on said protocol data unit and maintaining at least one queue structure for transmission with a transmit queue subsystem.

10. The method as recited in claim 9 wherein said maintaining said linked list further comprises maintaining a linked list of said at least two non-contiguous blocks.

11. The method as recited in claim 8 wherein said virtual segmentation is performed by a stream editor subsystem.

12. The method as recited in claim 11 wherein said virtual segmentation further comprises converting between a first protocol and a second protocol.

13. The method as recited in claim 11 wherein said virtual segmentation further comprises generating a validity check selected from the group consisting of:

a cyclic redundancy check (CRC),

a CRC for asynchronous transfer mode (ATM) adaptive layer 5 (AAL5) over ATM, and

a CRC-10 for operation, administration, maintenance (OAM) cells.

14. The method as recited in claim 9 wherein said receiving, assembling and performing further comprises processing a plurality of interleaved portions of different protocol data units.

15. A routing switch processor, comprising:

a protocol data unit receiver subsystem including an assembler subsystem and a transmit queue subsystem, said assembler subsystem being configured to:

receive at least a portion of payload data of a protocol data unit, and assemble said protocol data unit, and

receive routing information associated with said protocol data unit, said routing information including a port selected for said protocol data unit;

a memory configured to receive from said assembler subsystem said assembled protocol data unit, and to:

allocate space for said protocol data unit under control of said transmit queue subsystem, and

store said assembled protocol data unit in at least two non-contiguous memory blocks being interleaved with payload data from another different protocol data unit; and

a virtual segmentation subsystem, associated with said protocol data unit receiver subsystem, configured to perform virtual segmentation on said protocol data unit by segmenting said at least a portion of payload data when retrieved, said segmenting independent of reassembling an entirety of said protocol data unit.

16. The routing switch processor as recited in claim 15 wherein said transmit queue subsystem is configured to maintain a linked list associated with said protocol data unit, perform a function on said protocol data unit and maintain at least one queue structure for transmission.

17. The routing switch processor as recited in claim 15 wherein said assembler subsystem is further configured to store said at least a portion of payload data in said at least two non-contiguous blocks and said transmit queue subsystem is further configured to maintain a linked list of said at least two non-contiguous blocks.

18. The routing switch processor as recited in claim 15 wherein said virtual segmentation subsystem further includes a stream editor subsystem configured to perform said virtual segmentation.

19. The routing switch processor as recited in claim 18 wherein said stream editor subsystem is further configured to convert between a first protocol and a second protocol.

20. The routing switch processor as recited in claim 18 wherein said stream editor subsystem is further configured to generate a validity check selected from the group consisting of:

a cyclic redundancy check (CRC),

a CRC for asynchronous transfer mode (ATM) adaptive layer 5 (AAL5) over ATM, and

a CRC-10 for operation, administration, maintenance (OAM) cells.

Assignments (6)