IP Library Granted Patent US 7,290,071
Granted Patent B2
US 7,290,071 · App. 10/675,716 · Granted Oct 30, 2007

Processor with input data block discard mechanism for use in an oversubscription condition

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Quick Facts
Patent No.
US 7,290,071
App. No.
10/675,716
Granted
Oct 30, 2007
Kind
B2
Abstract

A processor includes a plurality of input ports, memory circuitry for storing data blocks associated with protocol data units (PDUs) and received by the processor at the input ports, and controller circuitry coupled to the memory circuitry. The controller circuitry is operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor. A discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular PDU is discarded. One or more additional data blocks received at the given input port for the particular PDU are discarded based at least in part on the discarded data block indicator. The oversubscription condition may thereby be overcome in a manner which advantageously minimizes the number of received PDUs that are corrupted through discarded data blocks.

Claims (33)

1. A processor comprising:

a plurality of input ports;

memory circuitry for storing data blocks associated with protocol data units and received by the processor at the input ports; and

controller circuitry coupled to the memory circuitry and operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor;

wherein a discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular protocol data unit is discarded;

wherein one or more additional data blocks received at the given input port for the particular protocol data unit are discarded based at least in part on the discarded data block indicator; and

wherein the controller circuitry is operative to maintain separate discarded data block indicators for respective ones of the plurality of input ports.

2. The processor of claim 1 wherein the controller circuitry sets the discarded data block indicator for the given input port to a first value when a first data block of the particular protocol data unit is discarded.

3. The processor of claim 2 wherein the controller circuitry is configured to automatically discard any remaining data blocks of the particular protocol data unit that are received at the given input port while the discarded data block indicator is set to the first value.

4. The processor of claim 2 wherein after a final data block of the particular protocol data unit is received at the given input port while the discarded data block indicator for the given input port is set to the first value, the controller circuitry is operative to enqueue the particular protocol data unit in a protocol data unit buffer of the memory circuitry.

5. The processor of claim 4 wherein the particular protocol data unit is enqueued with an associated error flag set.

6. The processor of claim 5 being further operative to initiate a clean-up operation for the protocol data unit based at least in part on the associated error flag.

7. The processor of claim 1 wherein the discarded data block indicator for the given input port comprises a single bit.

8. The processor of claim 7 wherein the single bit being at a first logic level indicates that at least one data block received at the given input port has been discarded for a corresponding protocol data unit, and the single bit being at a second logic level indicates that no data block received at the given input port has yet been discarded for the corresponding protocol data unit.

9. The processor of claim 1 wherein a given one of the discarded data block indicators indicates whether or not at least one data block received at the corresponding input port has been discarded.

10. The processor of claim 1 wherein the oversubscription condition is overcome by discarding only data blocks received at the given input port, and associated with the particular protocol data unit.

11. The processor of claim 1 wherein the received protocol data units are associated with frame-based data.

12. The processor of claim 1 wherein at least one of the input ports comprises a physical input port of the processor.

13. The processor of claim 1 wherein at least one of the input ports comprises a logical input port of the processor.

14. The processor of claim 1 wherein the protocol data unit comprises a packet.

15. The processor of claim 1 wherein the processor is configured to provide an interface for communication of the received protocol data units between a network and a switch fabric.

16. The processor of claim 1 wherein the processor comprises a network processor.

17. The processor of claim 1 wherein the processor is configured as an integrated circuit.

18. A method for use in a processor comprising a plurality of input ports for receiving data blocks associated with protocol data units, the method comprising the steps of:

discarding certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor; and

generating a discarded data block indicator for a given one of the input ports if a data block received at the given input port for a particular protocol data unit is discarded;

wherein one or more additional data blocks received at the given input port for the particular protocol data unit are discarded based at least in part on the discarded data block indicator; and

wherein separate discarded data block indicators are maintained for respective ones of the plurality of input ports.

19. An article of manufacture comprising a machine-readable storage medium having program code stored thereon for use in a processor comprising a plurality of input ports for receiving data blocks associated with protocol data units, the program code when executed in the processor implementing the steps of:

discarding certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor; and

generating a discarded data block indicator for a given one of the input ports if a data block received at the given input port for a particular protocol data unit is discarded;

wherein one or more additional data blocks received at the given input port for the particular protocol data unit are discarded based at least in part on the discarded data block indicator; and

wherein separate discarded data block indicators are maintained for respective ones of the plurality of input ports.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
CERTIFICATE OF CONVERSION Recorded Oct 19, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034014/0846 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2003
From: UTLEY, ROBERT H.
To: AGERE SYSTEMS INC.
Reel/Frame 014565/0435 →