System for bit-rate controlled digital stream playback and method thereof
View Patent ↗A system and methods are provided for a controlled transfer of a portion of a data stream between a digital storage media and a corresponding stream decoder. A data stream stored in digital storage media is accessed through an application. A FIFO is used to provide a buffer to the stream decoder. The application monitors the FIFO to determine when to send data related to the data stream from the digital storage media. The data is transferred to the buffer and passed to the stream decoder. A counter is used for dictating a period of time between sending segments of the data stored in the FIFO to the stream decoder. The rate of transfer to the stream decoder is adjusted through the counter to match a desired bit-rate associated with the data stream.
1. A method of comprising:
providing a portion of data in response to a counter value being reached, wherein the counter value is stored in a counter that is being incremented at a predetermined rate;
determining a current bit rate;
determining a desired bit rate over an amount of time;
determining a running average based on the current bit rate and the desired bit rate, wherein the running average is further based on a difference between a plurality of desired bit rates and current bit rates; and
setting the counter value based on the running average.
2. The method of claim 1 , wherein determining and setting are repeated at a predetermined interval rate.
3. The method of claim 2 , wherein the predetermined interval less than approximately 150 milliseconds.
4. The method of claim 2 , wherein the predetermined interval less than approximately 10 milliseconds.
5. The method of claim 1 , wherein setting the counter value includes using the running average to access a counter value stored in a table.
6. The method of claim 1 , wherein setting the counter value includes using the running average in an equation to determine the counter value.
7. The method of claim 1 , wherein the data is a portion of a packetized multimedia data stream.
8. The method of claim 1 , wherein the portion of data is a data word having a predetermined width.
9. The method of claim 1 , wherein the counter value is stored in a register of a first data processor, and setting the counter is performed by a host data processor that is different than the first data processor.
10. The method of claim 1 further including initializing the counter value to a first count based on a calculated time difference, wherein the calculated time difference is based on clock values stored in the data.
11. The method of claim 10 , wherein the first count is further based upon an amount of data stored between the clock values used to determine the time difference.
12. The method of claim 10 , wherein providing includes providing the portion of data to an MPEG audio decoder.
13. The method of claim 10 , wherein providing includes providing the portion of data to the MPEG video decoder.
14. A method of comprising:
reading a portion of data in response to a counter value being reached, wherein the counter value is stored in a counter that is incremented at a predetermined rate;
determining a current bit rate;
determining a desired bit rate over an amount of time;
determining a difference between the current bit rate and the desired bit rate;
increasing the counter value when the difference is greater than a predefined value; and
decreasing the counter value when the difference is negative.
15. The method of claim 14 , wherein the data is a portion of a packetized multimedia data stream.
16. The method of claim 14 , wherein the portion of data is a data word having a predetermined width.
17. The method of claim 14 , wherein setting the counter is repeated at a rate less than the predetermined amount of time.
18. The method of claim 14 , wherein setting the counter occurs at a repeated interval.
19. A system comprising:
a system bus port to couple to a system bus;
a system clock;
a memory configured as a first in first out memory (FIFO) coupled to a data holding register;
a first register coupled to the memory to store a current write location of the memory;
a second register coupled to the memory to store a current read location of the memory; and
a leak rate controller coupled to the memory to control a rate at which data is read from the memory, the leak rate controller further including
a data rate monitor to determine a current data rate;
a counter coupled to the system clock to provide a read signal when a predefined value is met, wherein the read signal is for accessing data stored in the memory.
20. The system of claim 19 , wherein the leak rate controller further includes a filter coupled to the data rate monitor to determine a running average of a difference between the current data rate and a desired data rate.
21. The system of claim 19 further comprising an audio decoder coupled to the memory.
22. The system of claim 20 further comprising a video decoder coupled to the memory.
23. The system of claim 19 further comprising a video decoder coupled to the memory.