Patent Application
Utility
App. No. 09/812,947
· Confirmation No. 5269
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND EXPOSURE METHOD
Inventor:
Hiroshi Takenaka
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-12-16 | PA.. |
Power of Attorney | 16 | View | |
| 2003-05-22 | PA.. |
Power of Attorney | 4 | View | |
| 2001-03-27 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-03-27 | ADS |
Application Data Sheet | 1 | View | |
| 2001-03-27 | SPEC |
Specification | 38 | View | |
| 2001-03-27 | CLM |
Claims | 4 | View | |
| 2001-03-27 | ABST |
Abstract | 1 | View | |
| 2001-03-27 | DRW |
Drawings-only black and white line drawings | 6 | View |
Inventors
Hiroshi Takenaka
Nagaokakyo-shi, JAPAN
Attorneys & Agents of Record
Classification
USPC
716/13
H10W20/40
Y10S438/942
Y10S438/949
Prosecution
- Examiner
- BOWERS, BRANDON
- Art Unit
- 2851
- Docket No.
- 0819-530
- Confirmation No.
- 5269
Foreign Priority
2000-085775
·
2000-03-27
·
JAPAN
Publication
- Pub. No.
- US20010052603A1
- Pub. Date
- 2001-12-20
Patent Term Adjustment
0days
MERGER
Recorded 2002-10-29
from
TAKENAKA, HIROSHI
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-07-20
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Quick Facts
- App. No.
- 09/812,947
- Filed
- 2001-03-27
- Granted
- 2004-04-20
- Pub. No.
- US20010052603A1
- Examiner
- BOWERS, BRANDON
- Art Unit
- 2851
- PTA
- 0 days
External Links